公开(公告)号：US06465292B2

公开(公告)日：2002-10-15

申请号：US10061211

申请日：2002-02-04

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L218234

CPC分类号： H01L29/78696 ,  H01L21/76297 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/404 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/78612 ,  H01L2924/0002 ,  H01L2924/00

摘要： An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. An FS isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes two edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of a prescribed region is smaller than a channel length at the central portion.

摘要翻译： 在硅衬底上形成SOI层，其间具有掩埋绝缘层。 形成SOI-MOSFET，其包括形成为在SOI层处限定沟道形成区域的漏极区域和源极区域，并且包括与沟道形成区域相对的栅极电极层，其间具有绝缘层。 FS隔离结构被形成为具有与漏极区域和源极区域的边缘部分附近的SOI层的区域相对的FS板，并且通过施加规定的方式将SOI-MOSFET与其它元件电隔离 将FS板的电位固定在与FS板相对的SOI层的区域的电位上。 通道形成区域包括两侧的两个边缘部分和沿通道宽度方向的边缘部分之间的中心部分，并且在规定区域的边缘处的通道长度小于中心部分处的通道长度。

公开(公告)号：US06424010B1

公开(公告)日：2002-07-23

申请号：US09169903

申请日：1998-10-09

申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L2976

摘要： An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.

公开(公告)号：US06436792B1

公开(公告)日：2002-08-20

申请号：US09325644

申请日：1999-06-04

申请人： Yasuo Yamaguchi ,  Shigenobu Maeda ,  Yuuichi Hirano

发明人： Yasuo Yamaguchi ,  Shigenobu Maeda ,  Yuuichi Hirano

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76291

摘要： A silicon oxide film (6aa) is formed on an upper surface of an SOI layer (3), a silicon nitride film (6bb) is formed on the silicon oxide film (6aa), and a silicon oxide film (6cc) is formed on the silicon nitride film (6bb). Using the silicon nitride film (6bb) as an etch stopper, anisotropic dry etching is performed on the silicon oxide film (6cc) in first and second device formation regions. Then, using the silicon oxide film (6aa) as an etch stopper, anisotropic dry etching is performed on the silicon nitride film (6bb) in the first and second device formation regions. The silicon oxide film (6aa) in the first and second device formation regions is removed by wet etching using hydrofluoric acid to expose the upper surface of the SOI layer (3). A method of manufacturing a semiconductor device is provided which is capable of avoiding the formation of a damaged layer in a main surface of an SOI substrate when such a device isolation structure is formed.

摘要翻译： 在SOI层（3）的上表面上形成氧化硅膜（6aa），在氧化硅膜（6aa）上形成氮化硅膜（6bb），在氧化硅膜（6a）上形成氧化硅膜（6cc） 氮化硅膜（6bb）。 使用氮化硅膜（6bb）作为蚀刻停止层，对第一和第二器件形成区域中的氧化硅膜（6cc）进行各向异性干蚀刻。 然后，使用氧化硅膜（6aa）作为蚀刻停止层，对第一和第二器件形成区域中的氮化硅膜（6bb）进行各向异性干蚀刻。 通过使用氢氟酸的湿蚀刻除去第一和第二器件形成区域中的氧化硅膜（6aa），以暴露SOI层（3）的上表面。 提供一种制造半导体器件的方法，其能够避免在形成器件隔离结构时在SOI衬底的主表面中形成受损层。

公开(公告)号：US5885858A

公开(公告)日：1999-03-23

申请号：US4169

申请日：1998-01-02

申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78678

摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。

公开(公告)号：US5440168A

公开(公告)日：1995-08-08

申请号：US198058

申请日：1994-02-18

申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/00 ,  H01L29/78

CPC分类号： H01L29/66765 ,  H01L29/78678

摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A second silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6). In addition, the thin-film transistor includes a semiconductor layer covering a gate electrode. The semiconductor layer includes source, drain and active regions. The active region preferably includes a smaller amount of fluorine than the gate electrode.

摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置第二氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。 此外，薄膜晶体管包括覆盖栅电极的半导体层。 半导体层包括源极，漏极和有源区。 有源区优选包括比栅电极少的氟。

公开(公告)号：US6103556A

公开(公告)日：2000-08-15

申请号：US228234

申请日：1999-01-11

申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/31

CPC分类号： H01L29/66765 ,  H01L29/78678

摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。

公开(公告)号：US06414353B1

公开(公告)日：2002-07-02

申请号：US09265697

申请日：1999-03-10

申请人： Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L2900

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78621

摘要： An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

摘要翻译： SOI层形成得很厚，使得在浮动和零电位的条件下，体区域未完全耗尽。 当MOSFET工作时，通过体电极将负电位施加到身体区域。 因此，身体区域完全耗尽。 MOSFET等效于PD模式的常规MOSFET关于SOI层的厚度，并且相当于FD模式的MOSFET的操作。 因此，源极/漏极区域中的低电阻，容易形成主电极的接触孔和硅化物层的稳定性等PD模式MOSFET的优点以及诸如优异的开关特性的FD模式MOSFET的优点 兼容实施。

公开(公告)号：US5981990A

公开(公告)日：1999-11-09

申请号：US607046

申请日：1996-02-26

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Hirotada Kuriyama

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Hirotada Kuriyama

IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/786 ,  H01L27/108

CPC分类号： H01L27/11 ,  H01L27/1108 ,  Y10S257/903

摘要： In a memory cell of an SRAM, a load transistor has a pair of source/drain regions formed to define a channel region, and a gate electrode layer being opposite to the channel region with an insulating layer therebetween. A VVP layer is formed to sandwich the channel region with the gate electrode layer to be opposite to channel region with an insulating layer therebetween. This VVP layer is provided such that GND potential is applied when active and Vcc potential is applied during standby. Thus, a large ON current can be implemented while maintaining a small OFF current of a TFT, even when the power supply voltage is made lower due to reduction in voltage.

摘要翻译： 在SRAM的存储单元中，负载晶体管具有形成为限定沟道区的一对源极/漏极区，以及与沟道区相对的栅极电极层，其间具有绝缘层。 形成VVP层，以使沟道区域与栅极电极层夹在与沟道区相对的位置，其间具有绝缘层。 提供这个VVP层，使得在待机期间施加有源和Vcc电位时施加GND电位。 因此，即使当由于电压降低使电源电压降低时，也可以在保持TFT的小的截止电流的同时实现大的导通电流。

公开(公告)号：US06492690B2

公开(公告)日：2002-12-10

申请号：US09366732

申请日：1999-08-04

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L27088

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： According to a semiconductor device and a method of manufacturing the same, a trade-off relationship between threshold values and a diffusion layer leak is eliminated and it is not necessary to form gate oxide films at more than one stages. Since impurity dose are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), impurity concentration in the gate electrodes (4A to 4C) are different from each other. The impurity concentration in the gate electrodes are progressively lower in the order of higher threshold values which are expected.

摘要翻译： 根据半导体器件及其制造方法，消除了阈值和扩散层泄漏之间的权衡关系，并且不需要在多于一个阶段形成栅极氧化膜。 由于杂质剂量在N沟道型MOS晶体管（T41〜T43）的栅电极（4A〜4C）之间彼此不同，所以栅电极（4A〜4C）中的杂质浓度彼此不同。 栅电极中的杂质浓度按预期的较高阈值的顺序逐渐降低。

公开(公告)号：US06815295B1

公开(公告)日：2004-11-09

申请号：US09429283

申请日：1999-10-28

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L21335

CPC分类号： H01L27/11526 ,  H01L21/76218 ,  H01L21/8234 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.

摘要翻译： 在根据本发明的半导体器件及其制造方法中，消除了阈值与扩散层泄漏之间的折衷关系，并且不需要在多于一个阶段形成栅极氧化膜。 由于在N沟道型MOS晶体管（T41〜T43）的栅电极（4A〜4C）之间氮的浓度彼此不同，因此导入氮区域（N1〜N3）的氮浓度因此不同 。 栅电极中的氮浓度按预期的较高阈值的顺序逐渐降低。