公开(公告)号：US5885858A

公开(公告)日：1999-03-23

申请号：US4169

申请日：1998-01-02

申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L29/78678

摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。

公开(公告)号：US5440168A

公开(公告)日：1995-08-08

申请号：US198058

申请日：1994-02-18

申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/00 ,  H01L29/78

CPC分类号： H01L29/66765 ,  H01L29/78678

摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A second silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6). In addition, the thin-film transistor includes a semiconductor layer covering a gate electrode. The semiconductor layer includes source, drain and active regions. The active region preferably includes a smaller amount of fluorine than the gate electrode.

摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置第二氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。 此外，薄膜晶体管包括覆盖栅电极的半导体层。 半导体层包括源极，漏极和有源区。 有源区优选包括比栅电极少的氟。

公开(公告)号：US6103556A

公开(公告)日：2000-08-15

申请号：US228234

申请日：1999-01-11

申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/31

CPC分类号： H01L29/66765 ,  H01L29/78678

摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。

公开(公告)号：US07164172B2

公开(公告)日：2007-01-16

申请号：US11061645

申请日：2005-02-22

申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

IPC分类号： H01L31/0392 ,  H01L29/04 ,  H01L29/06 ,  H01L31/036

CPC分类号： H01L29/045 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

摘要： There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a crystal direction of a support substrate (1) with a crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the crystal direction of the SOI layer (3). Since hole mobility is higher in the crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

摘要翻译： 提供一种半导体器件，其形成在半导体衬底上并且有效地利用了半导体衬底的特征，并且还提供了一种制造该半导体衬底的方法。 包括P型体层（3a）和与P型体层（3a）接触的体电压施加用P型有源层（6）的N沟道MOS晶体管形成在 被形成为使支撑衬底（1）的<110>晶体方向与SOI层（3）的<100>晶体方向对准的SOI衬底。 连接P型体层（3a）和用于体电压施加的P型有源层（6）的路径平行于SOI层（3）的<100>晶体方向排列。 由于在<100>晶体方向的空穴迁移率较高，所以在上述路径中可以减小寄生电阻（Ra，Rb）。 这加快了对P型体层（3a）的电压传输，并提高了P型体层（3a）中的电压固定能力。

公开(公告)号：US20060249756A1

公开(公告)日：2006-11-09

申请号：US11481799

申请日：2006-07-07

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L29/768

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： A semiconductor device includes a plurality of circuit portions of different functions each constructed by including a MOS transistor on an SOI substrate obtained by sequentially stacking a semiconductor substrate, a buried insulating film and a semiconductor layer. The semiconductor device includes first and second portions. The first circuit portion is isolated by being surrounded with a first insulating film provided on an upper portion of the semiconductor layer and a second insulating film penetrating the semiconductor layer to reach the buried insulating film.

摘要翻译： 半导体器件包括多个不同功能的电路部分，每个电路部分通过在通过顺序地堆叠半导体衬底，埋入绝缘膜和半导体层而获得的SOI衬底上包括MOS晶体管构成。 该半导体器件包括第一和第二部分。 第一电路部分通过被设置在半导体层的上部上的第一绝缘膜和穿过半导体层的第二绝缘膜包围而被隔离，以到达掩埋绝缘膜。

公开(公告)号：US20050184342A1

公开(公告)日：2005-08-25

申请号：US11108843

申请日：2005-04-19

申请人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

发明人： Yuuichi Hirano ,  Shigeto Maegawa ,  Toshiaki Iwamatsu ,  Takuji Matsumoto ,  Shigenobu Maeda ,  Yasuo Yamaguchi

IPC分类号： H01L21/762 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/336 ,  H01L21/00 ,  H01L21/331 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

摘要翻译： 在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。 电源线（21）形成在隔离绝缘膜（5）的上方。 在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。 换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面 ）。 利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

公开(公告)号：US20050167673A1

公开(公告)日：2005-08-04

申请号：US11078581

申请日：2005-03-14

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L27/11 ,  H01L27/12 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

摘要翻译： 提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。 漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。 漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。 定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

公开(公告)号：US20050156242A1

公开(公告)日：2005-07-21

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US06459125B2

公开(公告)日：2002-10-01

申请号：US09122863

申请日：1998-07-27

申请人： Shigenobu Maeda ,  Tadashi Nishimura ,  Kazuhito Tsutsumi ,  Shigeto Maegawa ,  Yuuichi Hirano

发明人： Shigenobu Maeda ,  Tadashi Nishimura ,  Kazuhito Tsutsumi ,  Shigeto Maegawa ,  Yuuichi Hirano

IPC分类号： H01L2900

CPC分类号： H01L23/556 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L29/786 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00

摘要： A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).

摘要翻译： 提供用于CSP安装的半导体器件，其避免由于α射线引起的误差并且具有高抗应力。 在半导体衬底（101）上形成掩埋氧化膜（107），在掩埋氧化膜（107）上形成具有SOI结构的MOS晶体管。 MOS晶体管包括形成在半导体层（120）中的源区和漏区（120a，120b）和栅电极（110）。 通过未示出的连接机构连接到源极和漏极区域（120a，120b）中的任何一个的铝焊盘（103）和在铝焊盘（103）的顶部具有开口的氮化硅膜（104） 形成在层间绝缘膜（108）上。 形成从铝焊盘（103）向氮化硅膜（104）的一端延伸的钛（105）层和镍层（106）。 焊料凸块（11）设置在镍层（106）上。

公开(公告)号：US06414353B1

公开(公告)日：2002-07-02

申请号：US09265697

申请日：1999-03-10

申请人： Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L2900

CPC分类号： H01L29/78615 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78621

摘要： An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

摘要翻译： SOI层形成得很厚，使得在浮动和零电位的条件下，体区域未完全耗尽。 当MOSFET工作时，通过体电极将负电位施加到身体区域。 因此，身体区域完全耗尽。 MOSFET等效于PD模式的常规MOSFET关于SOI层的厚度，并且相当于FD模式的MOSFET的操作。 因此，源极/漏极区域中的低电阻，容易形成主电极的接触孔和硅化物层的稳定性等PD模式MOSFET的优点以及诸如优异的开关特性的FD模式MOSFET的优点 兼容实施。