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    Method of manufacturing thin-film transistor
    1.
    发明授权
    Method of manufacturing thin-film transistor 失效
    制造薄膜晶体管的方法

    公开(公告)号：US5885858A

    公开(公告)日：1999-03-23

    申请号：US4169

    申请日：1998-01-02

    申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

    发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/84

    CPC分类号： H01L29/66765 ,  H01L29/78678

    摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6).

    摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。

    Thin-film transistor with suppressed off-current and V.sub.th
    2.
    发明授权
    Thin-film transistor with suppressed off-current and V.sub.th 失效
    具有抑制截止电流和Vth + B的薄膜晶体管

    公开(公告)号：US5440168A

    公开(公告)日：1995-08-08

    申请号：US198058

    申请日：1994-02-18

    申请人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

    发明人： Hisayuki Nishimura ,  Shigeto Maegawa ,  Shigenobu Maeda

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/00 ,  H01L29/78

    CPC分类号： H01L29/66765 ,  H01L29/78678

    摘要： A thin-film transistor (3, 5a, 5b and 5c) is covered with a first silicon nitride film (9) formed by an LPCVD method. A first silicon oxide film (6) is formed on the first silicon nitride film (9). A second silicon nitride film (7), i.e., passivation film which is formed by a plasma CVD method is provided on the first silicon oxide film (6). In addition, the thin-film transistor includes a semiconductor layer covering a gate electrode. The semiconductor layer includes source, drain and active regions. The active region preferably includes a smaller amount of fluorine than the gate electrode.

    摘要翻译： 薄膜晶体管（3,5a，5b和5c）被用LPCVD方法形成的第一氮化硅膜（9）覆盖。 在第一氮化硅膜（9）上形成第一氧化硅膜（6）。 在第一氧化硅膜（6）上设置第二氮化硅膜（7），即通过等离子体CVD法形成的钝化膜。 此外，薄膜晶体管包括覆盖栅电极的半导体层。 半导体层包括源极，漏极和有源区。 有源区优选包括比栅电极少的氟。

    Semiconductor device, method of manufacturing same and method of designing same
    6.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 失效
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US06953979B1

    公开(公告)日：2005-10-11

    申请号：US09466934

    申请日：1999-12-20

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor device and method of manufacturing the same
    7.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06882006B2

    公开(公告)日：2005-04-19

    申请号：US10188103

    申请日：2002-07-03

    申请人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Hirotada Kuriyama ,  Shigeto Maegawa

    发明人： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Hirotada Kuriyama ,  Shigeto Maegawa

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L27/11 ,  H01L27/12 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/092 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7827

    摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.

    摘要翻译： 可以获得占据小面积的场效应晶体管和使用其的半导体器件。 栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。 栅电极被第二层间绝缘膜覆盖。 提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。 接触孔的侧壁表面被栅极绝缘膜覆盖。 第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。 沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。 在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

    Semiconductor device and method of manufacturing same
    8.
    发明授权
    Semiconductor device and method of manufacturing same 失效
    半导体装置及其制造方法

    公开(公告)号：US06870226B2

    公开(公告)日：2005-03-22

    申请号：US10459490

    申请日：2003-06-12

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takuji Matsumoto

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/11 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H01L27/01

    CPC分类号： H01L29/045 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78687 ,  H01L29/78696

    摘要： There is provided a semiconductor device which is formed on a semiconductor substrate and allows effective use of the feature of the semiconductor substrate, and there is also provided a method of manufacturing the same. An N-channel MOS transistor including a P-type body layer (3a), and a P-type active layer (6) for body voltage application which is in contact with the P-type body layer (3a) are formed on an SOI substrate which is formed to align a crystal direction of a support substrate (1) with a crystal direction of an SOI layer (3). A path connecting the P-type body layer (3a) and the P-type active layer (6) for body voltage application is aligned parallel to the crystal direction of the SOI layer (3). Since hole mobility is higher in the crystal direction, parasitic resistance (Ra, Rb) can be reduced in the above path. This speeds up voltage transmission to the P-type body layer (3a) and improves voltage fixing capability in the P-type body layer (3a).

    摘要翻译： 提供一种半导体器件，其形成在半导体衬底上并且有效地利用了半导体衬底的特征，并且还提供了一种制造该半导体衬底的方法。 包括P型体层（3a）和与P型体层（3a）接触的体电压施加用P型有源层（6）的N沟道MOS晶体管形成在SOI 衬底，其被形成为使支撑衬底（1）的<110>晶体方向与SOI层（3）的<100>晶体方向对准。 连接P型体层（3a）和用于体电压施加的P型有源层（6）的路径平行于SOI层（3）的<100>晶体方向排列。 由于在<100>晶体方向的空穴迁移率较高，所以在上述路径中可以减小寄生电阻（Ra，Rb）。 这加快了P型体层（3a）的电压传输，提高了P型体层（3a）的电压固定能力。