System and Method for Performing Incremental Register Checkpointing in Transactional Memory
    91.
    发明申请
    System and Method for Performing Incremental Register Checkpointing in Transactional Memory 有权
    在事务性存储器中执行增量寄存器检查点的系统和方法

    公开(公告)号:US20120005461A1

    公开(公告)日:2012-01-05

    申请号:US12827842

    申请日:2010-06-30

    IPC分类号: G06F9/312

    摘要: Systems and methods described herein for performing incremental register checkpointing may employ a special register to indicate which registers have already been checkpointed. This register may include one bit per register. These systems may also include a special pointer register whose value identifies a location in user memory or in dedicated on-chip storage at which a copy of a register's value should be saved by a checkpointing operation. Only registers modified during speculative execution or execution of a transaction may be checkpointed (e.g., when register modifying instructions are encountered) and subsequently restored (e.g., due to misspeculation or transaction abort), rather than all of the registers of the processor. Each register may be checkpointed at most once for a given speculative episode or atomic transaction. Setting a bit in the special register may prevent checkpointing of the corresponding register. Setting all of the bits in the special register may disable checkpointing.

    摘要翻译: 本文描述的用于执行增量寄存器检查点的系统和方法可以使用特殊寄存器来指示哪些寄存器已经被检查点。 该寄存器可以包括每个寄存器一位。 这些系统还可以包括特殊的指针寄存器,其特征指针寄存器的值标识用户存储器中的位置或专用片上存储器,通过检查点操作应该保存寄存器值的副本。 只有在推测性执行或执行交易期间修改的寄存器可以是检查点(例如,当遇到寄存器修改指令时)并且随后恢复(例如,由于错误设置或事务中止)而不是处理器的所有寄存器。 对于给定的投机事件或原子事务,每个寄存器最多可以被检查点一次。 在特殊寄存器中设置一位可能会阻止相应寄存器的检查点。 设置特殊寄存器中的所有位可能会禁用检查点。

    Techniques for providing improved affinity scheduling in a multiprocessor computer system
    92.
    发明授权
    Techniques for providing improved affinity scheduling in a multiprocessor computer system 有权
    在多处理器计算机系统中提供改进的关联调度的技术

    公开(公告)号:US08051418B1

    公开(公告)日:2011-11-01

    申请号:US11084951

    申请日:2005-03-21

    申请人: David Dice

    发明人: David Dice

    IPC分类号: G06F9/46 G06F13/00

    CPC分类号: G06F9/5033

    摘要: Techniques for controlling a thread on a computerized system having multiple processors involve accessing state information of a blocked thread, and maintaining the state information of the blocked thread at current values when the state information indicates that less than a predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such techniques further involve setting the state information of the blocked thread to identify affinity for a particular processor of the multiple processors when the state information indicates that at least the predetermined amount of time has elapsed since the blocked thread ran on the computerized system. Such operation enables the system to place a cold blocked thread which shares data with another thread on the same processor of that other thread so that, when the blocked thread awakens and runs, that thread is closer to the shared data.

    摘要翻译: 用于控制具有多个处理器的计算机化系统上的线程的技术涉及访问被阻塞线程的状态信息,并且当状态信息指示自从该时间起经过了预定的一段时间时,将被阻塞的线程的状态信息保持在当前值 阻塞的线程在计算机化系统上运行。 这种技术进一步涉及当状态信息指示自阻塞的线程在计算机化系统上运行以来经过了至少预定的时间量时,设置阻塞线程的状态信息以识别对多个处理器的特定处理器的亲和性。 这样的操作使得系统能够将与另一个线程共享数据的冷的阻塞线程放置在该另一个线程的同一处理器上,使得当被阻塞的线程唤醒并运行时,该线程更接近共享数据。

    Method and System for Inter-Thread Communication Using Processor Messaging
    93.
    发明申请
    Method and System for Inter-Thread Communication Using Processor Messaging 有权
    使用处理器消息传递进行线程间通信的方法和系统

    公开(公告)号:US20100169895A1

    公开(公告)日:2010-07-01

    申请号:US12345179

    申请日:2008-12-29

    IPC分类号: G06F9/54

    摘要: In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.

    摘要翻译: 在共享内存计算机系统中,线程可以使用共享内存彼此进行通信。 接收线程可以重复轮询消息目标位置以检测消息的传递。 这种轮询可能导致各种系统总线和/或其他互连上的高速缓存一致性业务和/或拥塞。 用于处理器间通信的方法可以通过减少执行的读取的数量和/或传递消息所需的高速缓存一致性消息的数量来减少这种总线流量。 该方法可以包括读取消息目标位置的值一次的线程,并且通过检测指示这种修改的处理器间消息(例如高速缓存一致性消息)来确定该值已被修改。 在支持事务内存的系统中,线程可以使用事务存储器原语来检测高速缓存一致性消息。 这可以通过启动事务,读取目标内存位置和旋转直到事务中止来完成。

    ADAPTIVE SPIN-THEN-BLOCK MUTUAL EXCLUSION IN MULTI-THREADED PROCESSING
    94.
    发明申请
    ADAPTIVE SPIN-THEN-BLOCK MUTUAL EXCLUSION IN MULTI-THREADED PROCESSING 有权
    多线程处理中的自适应旋转相位互斥

    公开(公告)号:US20090328053A1

    公开(公告)日:2009-12-31

    申请号:US12554116

    申请日:2009-09-04

    申请人: David Dice

    发明人: David Dice

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526 G06F9/461

    摘要: Adaptive modifications of spinning and blocking behavior in spin-then-block mutual exclusion include limiting spinning time to no more than the duration of a context switch. Also, the frequency of spinning versus blocking is limited to a desired amount based on the success rate of recent spin attempts. As an alternative, spinning is bypassed if spinning is unlikely to be successful because the owner is not progressing toward releasing the shared resource, as might occur if the owner is blocked or spinning itself. In another aspect, the duration of spinning is generally limited, but longer spinning is permitted if no other threads are ready to utilize the processor. In another aspect, if the owner of a shared resource is ready to be executed, a thread attempting to acquire ownership performs a “directed yield” of the remainder of its processing quantum to the other thread, and execution of the acquiring thread is suspended.

    摘要翻译: 旋转和阻塞互斥中的旋转和阻塞行为的自适应修改包括将旋转时间限制为不超过上下文切换的持续时间。 此外,基于最近的旋转尝试的成功率,旋转与阻塞的频率被限制到期望的量。 作为替代方案,如果旋转不太可能成功,则旋转是绕过的,因为所有者不会在释放共享资源方面发展,如果所有者被阻塞或旋转本身,则会发生旋转。 在另一方面,旋转的持续时间通常是有限的,但如果没有其他线程准备好利用处理器,则允许更长的旋转。 在另一方面,如果共享资源的所有者准备好被执行,则尝试获得所有权的线程向其他线程执行其处理量子剩余部分的“定向收益”,并且暂停执行获取线程。

    Page-protection based memory access barrier traps
    95.
    发明申请
    Page-protection based memory access barrier traps 有权
    基于页面保护的内存访问障碍陷阱

    公开(公告)号:US20080172538A1

    公开(公告)日:2008-07-17

    申请号:US11654456

    申请日:2007-01-17

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0253

    摘要: A method, apparatus and computer program product for providing page-protection based memory access barrier traps is presented. A value for a user-mode bit (u-bit) is computed for each extant virtual page in an address space, the u-bit indicative that an object on the virtual page is being moved by a Garbage Collector process. An instruction is executed which causes an access protection fault. The state of the u-bit for the virtual page associated with the access protection fault is consulted when the access protection fault is encountered. Additionally, the access protection fault is translated into a user-trap (utrap) and the utrap is serviced when the u-bit is set.

    摘要翻译: 提出了一种用于提供基于页面保护的存储器访问障碍阱的方法,装置和计算机程序产品。 为地址空间中的每个现有虚拟页面计算用户模式位(u位)的值,表示虚拟页面上的对象正在被垃圾收集器进程移动的u位。 执行导致访问保护故障的指令。 当遇到访问保护故障时,将查阅与访问保护故障相关联的虚拟页面的u位状态。 另外,访问保护故障被转换为用户陷阱(utrap),并且当u位置1时,接口保护故障被服务。

    Methods and apparatus to implement parallel transactions
    96.
    发明申请
    Methods and apparatus to implement parallel transactions 审中-公开
    实现并行交易的方法和设备

    公开(公告)号:US20070198979A1

    公开(公告)日:2007-08-23

    申请号:US11475716

    申请日:2006-06-27

    申请人: David Dice Nir Shavit

    发明人: David Dice Nir Shavit

    IPC分类号: G06F9/46

    摘要: For each of multiple processes executing in parallel, as long as corresponding version information associated with a respective set of one or more shared variables used for computational purposes has not changed during execution of a respective transaction, results of the respective transaction can be globally committed to memory without causing data corruption. If version information associated with one or more respective shared variables (used to produce the transaction results) happens to change during a process of generating respective results, then a respective process can identify that another process modified the one or more respective shared variables during execution and that its transaction results should not be committed to memory. In this latter case, the transaction repeats itself until it is able to commit respective results without causing data corruption.

    摘要翻译: 对于并行执行的多个进程中的每一个,只要在用于计算目的的一个或多个共享变量的相应集合相关联的对应版本信息在相应事务的执行期间没有改变时,相应的事务的结果可以被全局地承诺 内存而不会导致数据损坏。 如果与一个或多个相应的共享变量(用于产生交易结果)相关联的版本信息在生成相应结果的过程中发生变化,则相应过程可以识别另一个进程在执行期间修改了一个或多个相应的共享变量,并且 它的交易结果不应该被提交到内存。 在后一种情况下,事务重复,直到它能够提交相应的结果而不会导致数据损坏。

    Methods and apparatus to implement parallel transactions
    97.
    发明申请
    Methods and apparatus to implement parallel transactions 有权
    实现并行交易的方法和设备

    公开(公告)号:US20070198792A1

    公开(公告)日:2007-08-23

    申请号:US11475262

    申请日:2006-06-27

    申请人: David Dice Nir Shavit

    发明人: David Dice Nir Shavit

    IPC分类号: G06F12/14

    摘要: A computer system includes multiple processing threads that execute in parallel. The multiple processing threads have access to a global environment including different types of metadata enabling the processing threads to carry out simultaneous execution depending on a currently selected type of lock mode. A mode controller monitoring the processing threads initiates switching from one type of lock mode to another depending on current operating conditions such as an amount of contention amongst the multiple processing threads to modify the shared data. The mode controller can switch from one lock mode another regardless of whether any of the multiple processes are in the midst of executing a respective transaction. A most efficient lock mode can be selected to carry out the parallel transactions. In certain cases, switching of lock modes causes one or more of the processing threads to abort and retry a respective transaction according to the new mode.

    摘要翻译: 计算机系统包括并行执行的多个处理线程。 多个处理线程可以访问包括不同类型的元数据的全局环境,使得处理线程可以根据当前选择的锁定模式类型执行同时执行。 监视处理线程的模式控制器根据当前操作条件(例如多个处理线程之间的争用量)来启动从一种类型的锁定模式切换到另一种类型的锁模式以修改共享数据。 模式控制器可以从一种锁定模式切换,而不管多个进程中的任何一个是否在执行相应的事务中。 可以选择最有效的锁定模式来执行并行事务。 在某些情况下,切换锁定模式会使一个或多个处理线程根据新模式中止并重试相应的事务。

    Methods and apparatus to implement parallel transactions
    98.
    发明申请
    Methods and apparatus to implement parallel transactions 有权
    实现并行交易的方法和设备

    公开(公告)号:US20070198781A1

    公开(公告)日:2007-08-23

    申请号:US11488618

    申请日:2006-07-18

    申请人: David Dice Nir Shavit

    发明人: David Dice Nir Shavit

    IPC分类号: G06F13/28 G06F12/00

    摘要: Cache logic associated with a respective one of multiple processing threads executing in parallel updates corresponding data fields of a cache to uniquely mark its contents. The marked contents represent a respective read set for a transaction. For example, at an outset of executing a transaction, a respective processing thread chooses a data value to mark contents of the cache used for producing a transaction outcome for the processing thread. Upon each read of shared data from main memory, the cache stores a copy of the data and marks it as being used during execution of the processing thread. If uniquely marked contents of a respective cache line happen to be displaced (e.g., overwritten) during execution of a processing thread, then the transaction is aborted (rather than being committed to main memory) because there is a possibility that another transaction overwrote a shared data value used during the respective transaction.

    摘要翻译: 与并行执行的多个处理线程中的相应一个相关联的缓存逻辑更新缓存的相应数据字段以唯一地标记其内容。 标记的内容表示交易的相应读取集合。 例如,在执行事务的开始时,相应的处理线程选择数据值来标记用于产生处理线程的事务结果的高速缓存的内容。 每次从主存储器读取共享数据时,高速缓存存储数据的副本,并将其标记为在执行处理线程期间被使用。 如果在执行处理线程期间相应的高速缓存线的唯一标记的内容恰好被移位(例如被重写),则事务被中止(而不是被提交到主存储器),因为存在另一个事务覆盖共享的可能性 在相应交易期间使用的数据值。

    Techniques for accessing a shared resource using an improved synchronization mechanism
    99.
    发明申请
    Techniques for accessing a shared resource using an improved synchronization mechanism 有权
    使用改进的同步机制访问共享资源的技术

    公开(公告)号:US20060031844A1

    公开(公告)日:2006-02-09

    申请号:US10861795

    申请日:2004-06-04

    IPC分类号: G06F9/46

    CPC分类号: G06F9/52

    摘要: A technique for accessing a shared resource of a computerized system involves running a first portion of a first thread within the computerized system, the first portion (i) requesting a lock on the shared resource and (ii) directing the computerized system to make operations of a second thread visible in a correct order. The technique further involves making operations of the second thread visible in the correct order in response to the first portion of the first thread running within the computerized system, and running a second portion of the first thread within the computerized system to determine whether the first thread has obtained the lock on the shared resource. Such a technique alleviates the need for using a MEMBAR instruction in the second thread.

    摘要翻译: 用于访问计算机化系统的共享资源的技术包括运行计算机化系统内的第一线程的第一部分,第一部分(i)请求锁定共享资源,以及(ii)引导计算机化系统使 第二个线程以正确的顺序可见。 该技术还涉及使第二线程的操作响应于在计算机化系统内运行的第一线程的第一部分以正确的顺序可见,并且在计算机化系统内运行第一线程的第二部分以确定第一线程 已获得共享资源上的锁定。 这种技术减轻了在第二线程中使用MEMBAR指令的需要。

    System and method providing an arrangement for efficiently emulating an operating system call

    公开(公告)号:US06530017B1

    公开(公告)日:2003-03-04

    申请号:US09062908

    申请日:1998-04-20

    IPC分类号: G06F1500

    CPC分类号: G06F9/45537 G06F9/4486

    摘要: An operating system call control subsystem is disclosed for use in a computer that includes a processor for processing a program, the program instructions of an operating system call instruction type identifying one of a plurality of types of operating system calls, each type of operating system call being associable with an operating system call type identifier value within a predetermined range of values. The operating system call control subsystem comprises a crossover table, an operating system call instruction type address resolution module, and an operating system call instruction type processing module. The crossover table has a number of entries corresponding to a predetermined fraction of the predetermined range, each entry in the crossover table having an instruction for enabling the processor to save a value corresponding to an offset of the entry into the crossover table. The operating system call instruction type address resolution module provides the instructions of the operating system call instruction type with respective target addresses that include an operating system call set identifier in a set of operating system call set identifiers, the number of operating system call set identifiers multiplied by the number of crossover table entries corresponding to the predetermined range and an offset value corresponding to an offset to an entry into the crossover table. The operating system call instruction type processing module, in response to the processor processing an instruction of the operating system call instruction type, (a) saves the operating system call set identifier from the target address, (b) selects one of the entries in the crossover table using the offset value of the target address, (c) processes the instruction from the selected entry of the crossover table to save the value corresponding to the offset of the selected entry in the crossover table, and (d) generates the operating system call type identifier value in connection with the saved operating system call set identifier and the saved value corresponding to the offset of the selected entry in the crossover table.