公开(公告)号：US20090171962A1

公开(公告)日：2009-07-02

申请号：US11967381

申请日：2007-12-31

Applicant: James R. Goodman ,  Mark S. Moir ,  Fu'ad W. F. Al Tabba' ,  Cong Wang

Inventor： James R. Goodman ,  Mark S. Moir ,  Fu'ad W. F. Al Tabba' ,  Cong Wang

IPC: G06F17/30

CPC classification number: G06F9/467

Abstract: Systems and methods for implementing and using nonblocking zero-indirection software transactional memory (NZSTM) are disclosed. NZSTM systems implement object-based software transactional memory that eliminates all levels of indirection except in the uncommon case of a conflict with an unresponsive thread. Shared data is co-located with a header in an NZObject, and is addressable at a fixed offset from the header. Conflicting transactions are requested to abort themselves without being forced to abort. NZObjects are modified in place when there are no conflicts, and when a conflicting transaction acknowledges the abort request. In the uncommon case, NZObjects are inflated to introduce a locator and some levels of indirection, and are restored to their un-inflated form following resolution of the conflict. In some embodiments, transactions are executed using best effort hardware transactional memory if it is available and effective, and software transactional memory if not, yielding a hybrid transactional memory system, NZTM.

Abstract translation: 公开了用于实现和使用非阻塞零间接软件事务存储器（NZSTM）的系统和方法。 NZSTM系统实现了基于对象的软件事务内存，消除了所有级别的间接，除非是与无响应线程冲突的罕见情况。 共享数据与NZObject中的头部位于一起，并且可以与头部固定的偏移量进行寻址。 要求冲突交易中止自己而不被迫中止。 当没有冲突时，NZObjects被修改就位，当冲突的事务确认中止请求时。 在不常见的情况下，NZObjects被膨胀以引入定位器和一定程度的间接性，并且在解决冲突之后恢复到它们没有膨胀的形式。 在一些实施例中，如果可用且有效，则使用尽力而为的硬件事务存储器来执行事务，如果不是，则使用软件事务存储器，产生混合事务存储器系统NZTM。

公开(公告)号：US07477169B2

公开(公告)日：2009-01-13

申请号：US11678825

申请日：2007-02-26

Applicant: Collis Q. Carter ,  Nicholas J. Chorney ,  James R. Goodman

Inventor： Collis Q. Carter ,  Nicholas J. Chorney ,  James R. Goodman

IPC: H03M7/00

CPC classification number: H04L7/041 ,  H04L1/0061 ,  H04L5/0092 ,  H04L25/4908 ,  H04L27/2607 ,  H04L2007/045 ,  H04N7/52 ,  H04N19/89 ,  H04N21/4122 ,  H04N21/436 ,  H04N21/4367 ,  H04N21/4408

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronization, transmitter/receiver synchronization or for other control signalling.

Abstract translation: 采用形式{k1-k2-k2-k1}的控制符号被插入到包括m位数据字的串行流中。 k1和k2是与m位数据字不同的预定义的m位控制字。 k1和k2之间的汉明距离至少为2.这样的控制符号可以在符号中存在一位错误或紧接在符号之前或之后的数据字的情况下被鲁棒地检测。 m位字可以是8B / 10B编码数据或定义的控制字。 控制符号可用于数据描绘，流同步，发射机/接收机同步或其他控制信令。

公开(公告)号：US07434006B2

公开(公告)日：2008-10-07

申请号：US11165688

申请日：2005-06-24

Applicant: Robert H. Beers ,  Herbert H. J. Hum ,  James R. Goodman

Inventor： Robert H. Beers ,  Herbert H. J. Hum ,  James R. Goodman

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0813

Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

Abstract translation: 冲突解决技术提供一致性，使得如果每个节点在该节点已经做出其自己的请求之后监视所有请求，则冲突请求者中的至少一个可以检测所有冲突。 如果一行处于“独占”，“修改”或“转发”状态，则在保存唯一副本的节点处解决冲突。 冲突解决的胜利者以及可能的失败者将冲突报告给家庭节点，该家庭节点对冲突报告和发出转发指令，以确保所有请求节点最终都接收到所请求的数据。 如果所请求的高速缓存行未被缓存或仅在共享状态下存在，则家庭节点提供缓存节点的副本并解决冲突。 在一个实施例中，在接收到确认消息之后的所有响应之后的停电时段允许所有冲突节点都知道它们涉及的冲突。

公开(公告)号：US07130969B2

公开(公告)日：2006-10-31

申请号：US10326234

申请日：2002-12-19

Applicant: Herbert H. J. Hum ,  James R. Goodman

Inventor： Herbert H. J. Hum ,  James R. Goodman

IPC: G06F12/00

CPC classification number: G06F12/0817 ,  G06F12/0813

Abstract: Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the agent. Because the import cache and the export directory only store data that has passed through the agent, not all data transferred within a system are tracked by a single import cache or export directory.

公开(公告)号：US07120762B2

公开(公告)日：2006-10-10

申请号：US10037041

申请日：2001-10-19

Applicant: Ravi Rajwar ,  James R. Goodman

Inventor： Ravi Rajwar ,  James R. Goodman

IPC: G06F12/14

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/69

Abstract: Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage.

公开(公告)号：US07111128B2

公开(公告)日：2006-09-19

申请号：US10324711

申请日：2002-12-19

Applicant: Herbert H. J. Hum ,  James R. Goodman

Inventor： Herbert H. J. Hum ,  James R. Goodman

IPC: G06F12/00

CPC classification number: G06F12/0813 ,  G06F12/0815 ,  G06F2212/2542

Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

Abstract translation: 本文描述的高速缓存一致性协议可用于维护系统的虚拟模型，其中虚拟模型不随系统配置改变而改变。 一般来说，虚拟模型是基于系统中的每个节点可以直接与系统中的其他节点通信的假设。 在一个实施例中，对于每个高速缓存行，高速缓存行的地址用于将节点指定为“家”节点，将所有其他节点指定为“对等”节点。 该协议指定一组消息，用于与线路的家庭节点通信，另一组消息用于与线路的对等节点进行通信。

公开(公告)号：US6161170A

公开(公告)日：2000-12-12

申请号：US296027

申请日：1999-04-21

Applicant: Douglas C. Burger ,  Stefanos Kaxiras ,  James R. Goodman

Inventor： Douglas C. Burger ,  Stefanos Kaxiras ,  James R. Goodman

IPC: G06F9/50 ,  G06F12/08 ,  G06F15/00

CPC classification number: G06F9/5016 ,  G06F9/50 ,  G06F12/0813

Abstract: A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

Abstract translation: 分布式存储器计算机架构将单独的存储器块与其自己的处理器相关联，每个处理器执行相同的程序。 从其本地存储器获取数据或指令的处理器还将获取的数据或指令广播到其他处理器，以减少他们请求此数据所需的时间。 指令和数据本地运行到一个处理器，提供整个系统捕获的改进的性能，其他处理器不执行本地数据或指令执行指令，并返回以在缓冲区中找到准备好的数据的能力 快速使用。

公开(公告)号：US4243358A

公开(公告)日：1981-01-06

申请号：US950456

申请日：1978-10-11

Applicant: Gaylord W. Carlock ,  William L. McKeown ,  James R. Goodman ,  Chester Skrodzki

Inventor： Gaylord W. Carlock ,  William L. McKeown ,  James R. Goodman ,  Chester Skrodzki

IPC: B64C27/58 ,  B64C27/605 ,  B64C27/72

CPC classification number: B64C27/605 ,  B64C27/72 ,  Y02T50/34

Abstract: A helicopter mast is driven by a transmission with a swashplate individually linked to pitch horns on each rotor blade. At least four actuators are coupled to the swashplate, three of which normally control the attitude and position of the swashplate. A separate power unit is provided for each actuator, each power unit being independently driven from the transmission. Means are then provided to shift control of the swashplate from one of the three actuators to a fourth actuator upon any one becoming disabled.

Abstract translation: 直升机桅杆由传动装置驱动，斜盘单独连接到每个转子叶片上的桨距角。 至少四个致动器联接到旋转斜盘，其中三个致动器通常控制斜盘的姿态和位置。 为每个致动器提供单独的动力单元，每个动力单元独立地从变速器驱动。 然后提供装置，以便在任何一个变得禁用时将斜盘的控制从三个致动器之一转换到第四致动器。

公开(公告)号：US20100287340A1

公开(公告)日：2010-11-11

申请号：US12843828

申请日：2010-07-26

Applicant: Ravi Rajwar ,  James R. Goodman

Inventor： Ravi Rajwar ,  James R. Goodman

IPC: G06F12/08 ,  G06F12/14

CPC classification number: G06F9/528 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/52 ,  G06F12/0808 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/128 ,  G06F12/1458 ,  G06F12/1475 ,  G06F2212/1041 ,  G06F2212/1052 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/69

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract translation: 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

公开(公告)号：US20100262893A1

公开(公告)日：2010-10-14

申请号：US12528712

申请日：2008-02-26

Applicant: Collis Q. Carter ,  Nicholas J. Chorney ,  James R. Goodman

Inventor： Collis Q. Carter ,  Nicholas J. Chorney ,  James R. Goodman

IPC: H03M13/19

CPC classification number: H04L7/041 ,  G09G2370/10 ,  H04L1/0061 ,  H04L1/0083 ,  H04L25/4908 ,  H04L2007/045 ,  H04N7/52 ,  H04N19/89 ,  H04N21/236 ,  H04N21/2383 ,  H04N21/6332

Abstract: Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronizaiton, transmitter/receiver synchronization or for other control signalling.

Abstract translation: 采用形式{k1-k2-k2-k1}的控制符号被插入到包括m位数据字的串行流中。 k1和k2是与m位数据字不同的预定义的m位控制字。 k1和k2之间的汉明距离至少为2.这样的控制符号可以在符号中存在一位错误或紧接在符号之前或之后的数据字的情况下被鲁棒地检测。 m位字可以是8B / 10B编码数据或定义的控制字。 控制符号可用于数据描绘，流同步，发射机/接收机同步或用于其他控制信令。