公开(公告)号：US08207757B1

公开(公告)日：2012-06-26

申请号：US13022231

申请日：2011-02-07

申请人： An Chen ,  Zoran Krivokapic

发明人： An Chen ,  Zoran Krivokapic

IPC分类号： H03K19/20

CPC分类号： H03K19/20 ,  H03K19/19

摘要： Apparatus and related fabrication and operating methods are provided for logic circuits that include ferromagnetic elements. An exemplary logic circuit includes a first ferromagnetic element having a first ferromagnetic layer, a second ferromagnetic element having a second ferromagnetic layer, and a transistor coupled to the first ferromagnetic element. The first transistor is configured to allow current to flow through the first ferromagnetic element. The current influences the magnetization direction of the first ferromagnetic layer, which, in turn, influences the magnetization direction of the second ferromagnetic layer.

摘要翻译： 为包括铁磁元件的逻辑电路提供装置和相关的制造和操作方法。 示例性逻辑电路包括具有第一铁磁层的第一铁磁元件，具有第二铁磁层的第二铁磁元件和耦合到第一铁磁元件的晶体管。 第一晶体管被配置为允许电流流过第一铁磁元件。 该电流影响第一铁磁层的磁化方向，这进而影响第二铁磁层的磁化方向。

公开(公告)号：US07994020B2

公开(公告)日：2011-08-09

申请号：US12176866

申请日：2008-07-21

申请人： Ming-ren Lin ,  Zoran Krivokapic ,  Witek Maszara

发明人： Ming-ren Lin ,  Zoran Krivokapic ,  Witek Maszara

IPC分类号： H01L21/76

CPC分类号： H01L21/823431 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

摘要： A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner.

摘要翻译： 提供了诸如FinFET器件结构的半导体器件结构的制造方法。 该方法开始于提供包括体半导体材料的衬底，由体半导体材料形成的第一导电鳍结构以及由体半导体材料形成的第二导电鳍结构。 第一导电鳍结构和第二导电鳍结构被间隙分开。 接下来，间隔件形成在间隙中并且与第一导电翅片结构和第二导电翅片结构相邻。 此后，蚀刻步骤使用间隔物作为蚀刻掩模来蚀刻体半导体材料，以在体半导体材料中形成隔离沟槽。 绝缘材料形成在隔离沟槽中，在间隔物之上，在第一导电鳍结构之上，并在第二导电鳍结构之上。 此后，介电材料的至少一部分和至少一部分间隔物被蚀刻掉以露出第一导电鳍结构的上部和第二导电翅片结构的上部，同时将介电材料保留在 隔离沟 按照这些步骤，以常规方式完成装置的制造。

公开(公告)号：US07973364B2

公开(公告)日：2011-07-05

申请号：US12072885

申请日：2008-02-27

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L27/12

CPC分类号： H01L29/105 ,  G11C11/404 ,  G11C2211/4016 ,  H01L21/2652 ,  H01L21/28114 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66545 ,  H01L29/7841 ,  H01L29/78603 ,  H01L29/78696

摘要： According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of the one-transistor memory cell in a bulk substrate underlying the buried oxide layer. The method further includes forming a charge trapping region in the buried oxide layer. The charge trapping region is formed at an interface between a silicon layer underlying the gate stack and the buried oxide layer. The charge trapping region causes the one-transistor memory cell to have an increased sensing margin. The method further includes forming a top gate of the one-transistor memory cell in the opening. Also disclosed is an exemplary one-transistor memory cell fabricated utilizing the exemplary disclosed method.

摘要翻译： 根据一个示例性实施例，用于制造单晶体管存储单元的方法包括通过去除绝缘体上硅（SOI）器件的栅堆叠的一部分来形成开口，其中SOI器件位于掩埋氧化物 层。 该方法还包括在掩埋氧化物层下面的大块衬底中形成单晶体管存储单元的底栅。 该方法还包括在掩埋氧化物层中形成电荷俘获区域。 电荷捕获区形成在栅极堆叠下面的硅层和掩埋氧化物层之间的界面处。 电荷捕获区域使得单晶体管存储单元具有增加的感测裕度。 该方法还包括在开口中形成单晶体管存储单元的顶栅。 还公开了利用示例性公开的方法制造的示例性单晶体管存储器单元。

公开(公告)号：US20110147709A1

公开(公告)日：2011-06-23

申请号：US12644980

申请日：2009-12-22

申请人： An Chen ,  Zoran Krivokapic

发明人： An Chen ,  Zoran Krivokapic

IPC分类号： H03K19/168

CPC分类号： H03K19/168 ,  B82Y10/00 ,  B82Y25/00

摘要： A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.

摘要翻译： 一个场耦合的纳米磁体包括至少一个元件，其具有与其它纳米磁体相同的各向异性能量。 信号可以从具有相对高各向异性能的第一输入纳米磁体通过链传播到输出纳米磁体。 输出纳米磁体可具有比其他纳米磁体相对较低的各向异性能量。 因此可以控制信号流动方向。 较高的各向异性能纳米磁体可以通过使用具有较高各向异性常数的铁磁体材料和/或配置有比其它元件更大的体积来实现。 较低各向异性能量磁体可以通过使用具有较低各向异性常数的铁磁体材料和/或配置为具有比其它元件更小的体积来获得。 也可以利用具有两个不同取向的纳米磁体的三维几何形状来实现逻辑信号流控制。

公开(公告)号：US07871873B2

公开(公告)日：2011-01-18

申请号：US12413174

申请日：2009-03-27

申请人： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

发明人： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/66795

摘要： A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

摘要翻译： 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US07858990B2

公开(公告)日：2010-12-28

申请号：US12201851

申请日：2008-08-29

申请人： An Chen ,  Zoran Krivokapic

发明人： An Chen ,  Zoran Krivokapic

IPC分类号： H01L29/15

CPC分类号： H01L29/78684 ,  H01L29/1606 ,  H01L29/66742 ,  H01L29/7781

摘要： A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.

摘要翻译： 基于石墨烯的器件形成有一层或多层材料中的沟槽，沟槽内的石墨烯层，以及石墨烯层和沟槽内的器件结构。 制造技术包括形成由一层或多层材料限定的沟槽，在沟槽内形成石墨烯层，并在石墨烯层和沟槽内形成器件结构。

公开(公告)号：US07781810B1

公开(公告)日：2010-08-24

申请号：US11538217

申请日：2006-10-03

申请人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

发明人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L29/72

CPC分类号： H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

摘要： A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

摘要翻译： 一种装置包括鳍片，第一栅极和第二栅极。 第一门形成在鳍片的第一侧附近，并且包括具有第一厚度并且具有与鳍片的上表面基本共面的上表面的第一材料层。 所述第二浇口邻近所述翅片的与所述第一侧相对的第二侧形成，并且包括具有第二厚度并具有与所述翅片的上表面基本共面的上表面的第二材料层，其中所述第一厚度 并且第二厚度基本上等于翅片的高度。

公开(公告)号：US20090256206A1

公开(公告)日：2009-10-15

申请号：US12082637

申请日：2008-04-10

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L21/336

CPC分类号： H01L29/78684 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7841 ,  H01L29/7842

摘要： According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.

摘要翻译： 根据一个示例性实施例，绝缘体上的p沟道锗（GOI）一个晶体管存储单元包括在体衬底上形成的掩埋氧化物（BOX）层，以及形成在位于锗层上方的栅极电介质层上的栅极 掩埋氧化物（BOX）层。 源极区域形成在与栅极下方的沟道区相邻的锗层中，并且覆盖BOX层，并且在与沟道区相邻的锗层中形成漏极区。 源极区和漏极区注入p型掺杂剂。 在一个实施例中，p沟道GOI一晶体管存储单元被实现为无电容动态随机存取存储器（DRAM）单元。 在一个实施例中，多个p沟道GOI一个晶体管存储单元包括在存储器阵列中。

公开(公告)号：US20090212363A1

公开(公告)日：2009-08-27

申请号：US12072885

申请日：2008-02-27

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L27/12 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/105 ,  G11C11/404 ,  G11C2211/4016 ,  H01L21/2652 ,  H01L21/28114 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66545 ,  H01L29/7841 ,  H01L29/78603 ,  H01L29/78696

摘要： According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of the one-transistor memory cell in a bulk substrate underlying the buried oxide layer. The method further includes forming a charge trapping region in the buried oxide layer. The charge trapping region is formed at an interface between a silicon layer underlying the gate stack and the buried oxide layer. The charge trapping region causes the one-transistor memory cell to have an increased sensing margin. The method further includes forming a top gate of the one-transistor memory cell in the opening. Also disclosed is an exemplary one-transistor memory cell fabricated utilizing the exemplary disclosed method.

摘要翻译： 根据一个示例性实施例，用于制造单晶体管存储单元的方法包括通过去除绝缘体上硅（SOI）器件的栅堆叠的一部分来形成开口，其中SOI器件位于掩埋氧化物 层。 该方法还包括在掩埋氧化物层下面的大块衬底中形成单晶体管存储单元的底栅。 该方法还包括在掩埋氧化物层中形成电荷俘获区域。 电荷捕获区形成在栅极堆叠下面的硅层和掩埋氧化物层之间的界面处。 电荷捕获区域使得单晶体管存储单元具有增加的感测裕度。 该方法还包括在开口中形成单晶体管存储单元的顶栅。 还公开了利用示例性公开的方法制造的示例性单晶体管存储器单元。

公开(公告)号：US20090146212A1

公开(公告)日：2009-06-11

申请号：US12368775

申请日：2009-02-10

申请人： Gen Pei ,  Zoran Krivokapic

发明人： Gen Pei ,  Zoran Krivokapic

IPC分类号： H01L27/06

CPC分类号： H01L27/11 ,  H01L29/7391

摘要： A negative differential resistance (NDR) diode and a memory cell incorporating that NDR diode are provided. The NDR diode comprises a p-type germanium region in contact with an n-type germanium region and forming a germanium pn junction diode. A first gate electrode overlies the p-type germanium region, is electrically coupled to the n-type germanium region, and is configured for coupling to a first electrical potential. A second gate electrode overlies the n-type germanium region and is configured for coupling to a second electrical potential. A third electrode is electrically coupled to the p-type germanium region and may be coupled to the second gate electrode. A small SRAM cell uses two such NDR diodes with a single pass transistor.

摘要翻译： 提供负差分电阻（NDR）二极管和包含该NDR二极管的存储单元。 NDR二极管包括与n型锗区接触并形成锗pn结二极管的p型锗区。 第一栅电极覆盖在p型锗区上，电耦合到n型锗区，并且被配置为耦合到第一电位。 第二栅电极覆盖在n型锗区上，并被配置成耦合到第二电位。 第三电极电耦合到p型锗区域并且可以耦合到第二栅电极。 一个小的SRAM单元使用两个这样的NDR二极管与单通道晶体管。