公开(公告)号：US08101486B2

公开(公告)日：2012-01-24

申请号：US12575344

申请日：2009-10-07

申请人： Witold Maszara ,  Hemant Adhikari

发明人： Witold Maszara ,  Hemant Adhikari

IPC分类号： H01L21/8238 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

公开(公告)号：US20110237046A1

公开(公告)日：2011-09-29

申请号：US12749220

申请日：2010-03-29

申请人： Witold MASZARA ,  Robert J. MILLER

发明人： Witold MASZARA ,  Robert J. MILLER

IPC分类号： H01L21/762

CPC分类号： H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.

摘要翻译： 提供一种制造翅片半导体器件结构的方法。 该方法开始于提供具有体半导体材料的衬底。 该方法继续通过从体半导体材料形成半导体鳍结构，沉积覆盖半导体鳍结构的绝缘材料，使得绝缘材料填充与半导体鳍结构相邻的空间，并将沉积的绝缘材料和半导体鳍结构平坦化为 创建一个平坦的表面。 此后，执行替换门程序以形成横向覆盖半导体鳍结构的栅极结构。

公开(公告)号：US20060180873A1

公开(公告)日：2006-08-17

申请号：US11307537

申请日：2006-02-11

申请人： Mario Pelella ,  William En ,  Eric Paton ,  Witold Maszara

发明人： Mario Pelella ,  William En ,  Eric Paton ,  Witold Maszara

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A suicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

摘要翻译： 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 硅化物层位于邻近栅极和栅极电介质的半导体衬底上。 硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。 浅层源极/漏极结在自对准层下面。 层间电介质位于半导体衬底之上，并且触点位于硅化物层的层间电介质中。

公开(公告)号：US06787436B1

公开(公告)日：2004-09-07

申请号：US10147382

申请日：2002-05-15

申请人： Matthew S. Buynoski ,  Witold Maszara

发明人： Matthew S. Buynoski ,  Witold Maszara

IPC分类号： H04L21425

CPC分类号： H01L21/28518

摘要： Methods for reducing the contact resistance presented by the interface between a silicide and a doped silicon region are presented. In a first method, a silicide layer and a doped silicon region form an interface. Either a damage-only species or a heavy, metal is implanted through the silicide layer into the doped silicon region immediately adjacent the interface. In a second method, a second metal is added to the refractory metal before formation of the silicide. After annealing the refractory metal and the doped silicon region, the second metal diffuses into the doped silicion region immediately adjacent the interface without forming additional phases in the silicide.

摘要翻译： 提出了降低由硅化物和掺杂硅区域之间的界面呈现的接触电阻的方法。 在第一种方法中，硅化物层和掺杂的硅区形成界面。 将仅有损坏的物质或重的金属通过硅化物层注入到与界面紧邻的掺杂硅区域中。 在第二种方法中，在形成硅化物之前，将第二种金属加入难熔金属中。 在难熔金属和掺杂硅区域退火之后，第二金属扩散到紧邻界面的掺杂硅化物区域，而不在硅化物中形成附加相。

公开(公告)号：US20050121731A1

公开(公告)日：2005-06-09

申请号：US10727999

申请日：2003-12-03

申请人： Witold Maszara

发明人： Witold Maszara

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/78 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628

摘要： A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

摘要翻译： 提供了一种形成具有半导体衬底的突点连接器件的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在与栅极和栅极电介质相邻的半导体衬底上形成侧壁间隔物。 通过在邻近侧壁间隔物的半导体衬底上选择性外延生长形成增厚层。 在增稠层的至少一部分形成凸起的源/漏掺杂剂注入区。 在升高的源极/漏极掺杂剂注入区域的至少一部分中形成硅化物层，以在硅化物层下面形成源极/漏极区域，其从硅化物层富集掺杂剂。 在硅化物层上沉积电介质层，然后在电介质层中形成接触到硅化物层。

公开(公告)号：US06274915B1

公开(公告)日：2001-08-14

申请号：US09225646

申请日：1999-01-05

申请人： Srinath Krishnan ,  Ming-Yin Hao ,  David Bang ,  Witold Maszara

发明人： Srinath Krishnan ,  Ming-Yin Hao ,  David Bang ,  Witold Maszara

IPC分类号： H01L2976

CPC分类号： H01L29/4916 ,  H01L29/1033

摘要： A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1×1019 and 5×1019 atoms/cm3.

摘要翻译： MOS晶体管的设计故意使用多晶硅栅电极中的耗尽来改善电路性能。 常规的晶体管设计旨在最小化多晶硅栅电极的耗尽以增加驱动电流。 根据本发明的实施例，大于常规电平的栅电极的适当耗尽量同时提供期望的驱动电流同时最小化电路延迟。 根据另一方面，通过调整沟道区域中的掺杂水平来改善电路性能，以将阈值电压维持在与多晶硅栅电极中的最小耗尽所达到的阈值电压相同的水平。 还提供了一种制造包括具有增加的耗尽的多晶硅栅电极的MOS器件的方法。 使用自对准掺杂工艺，其中多晶硅栅极，源极区域和漏极区域被同时注入到掺杂剂浓度为1×1019至5×1019原子/ cm3之间。

公开(公告)号：US08716074B2

公开(公告)日：2014-05-06

申请号：US13611193

申请日：2012-09-12

申请人： Witold Maszara ,  Hemant Adhikari

发明人： Witold Maszara ,  Hemant Adhikari

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

摘要翻译： 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层，并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模，并使用鳍状图案掩模作为蚀刻掩模，各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

公开(公告)号：US20120193751A1

公开(公告)日：2012-08-02

申请号：US13015857

申请日：2011-01-28

申请人： Hirohisa Kawasaki ,  Basker Veeraraghavan ,  Hemant Adhikari ,  Witold Maszara

发明人： Hirohisa Kawasaki ,  Basker Veeraraghavan ,  Hemant Adhikari ,  Witold Maszara

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.

摘要翻译： 提供制造散热片和包含散热片的半导体结构的方法。 所述方法包括在半导体衬底上形成多层结构。 多层结构包括半导体衬底上的第一层，第一层上的第二层和第二层上的第三层。 该方法还包括去除半导体衬底的上部和多层结构的部分以形成半导体衬底的鳍片和多层结构的部分。 此外，该方法包括选择性地氧化第一层，同时氧化第二层，第三层小于第一层的氧化。 可以在间隙填充凹部之前或间隙填充凹部之后进行氧化。

公开(公告)号：US08084330B2

公开(公告)日：2011-12-27

申请号：US12560938

申请日：2009-09-16

申请人： Witold Maszara

发明人： Witold Maszara

IPC分类号： H01L21/00

CPC分类号： H01L29/66795 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78654

摘要： Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the step of producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers laterally adjacent the gate stack. The method further includes the steps of amorphizing the S/D regions, depositing a silicide-forming material over the amorphized S/D regions, and heating the partially-completed semiconductor device to a predetermined temperature at which the silicide-forming material reacts with the amorphized S/D regions.

摘要翻译： 提供了制造半导体器件的方法的实施例。 在一个实施例中，该方法包括产生部分完成的半导体器件的步骤，该半导体器件包括衬底，源极/漏极（S / D）区域，S / D区域之间的沟道区域，沟道区域上的栅极堆叠，以及 横向隔离件横向邻近门堆叠。 该方法还包括以下步骤：使S / D区域非晶化，在非晶化S / D区域上沉积硅化物形成材料，并将部分完成的半导体器件加热至预定温度，在该温度下硅化物形成材料与 非晶化S / D区域。

公开(公告)号：US20080054316A1

公开(公告)日：2008-03-06

申请号：US11926655

申请日：2007-10-29

申请人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。