公开(公告)号：US20090256640A1

公开(公告)日：2009-10-15

申请号：US12100011

申请日：2008-04-09

Applicant: Peter T. A. Reilly ,  Hideya Koizumi

Inventor： Peter T. A. Reilly ,  Hideya Koizumi

IPC: H03B27/00

CPC classification number: G06F1/0328

Abstract: Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Abstract translation: 使用一组两个耦合的直接数字合成（DDS）电路产生可编程时钟波形的无抖动转换。 第一DDS电路中的第一相位累加器在第二DDS电路中的第二相位累加器之前的DDS电路中运行至少一个公共参考时钟的周期。 当从第一相位累加器检测到相位周期开始的相变时，计算第一和第二相位累加器的第一相位偏移字和第二相位偏移字并将其加载到第一和第二DDS电路中。 可编程时钟波形用作RAM地址控制器的时钟输入。 提供了任意波形的频率上明确定义的无抖动转换，其与来自第二DDS电路的DDS输出信号的相位周期的开始一致。

公开(公告)号：US07336748B2

公开(公告)日：2008-02-26

申请号：US10744039

申请日：2003-12-23

Applicant: Jason Messier

Inventor： Jason Messier

IPC: H04L7/00

CPC classification number: G06F1/0328 ,  H03L7/00

Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.

Abstract translation: 一种使用直接数字合成产生光谱纯，敏捷时钟的测试系统。 时钟用于自动测试系统中的模拟和数字仪器。 DDS电路与测试仪系统时钟同步，因为它是由系统时钟产生的DDS时钟计时的。 通过使用跟踪累积相位相对于系统时钟的并行累加器来减少累积相位误差。 在重合点，DDS累加器中的累加相复位为系统累加器中的值。

公开(公告)号：US07281025B2

公开(公告)日：2007-10-09

申请号：US10739761

申请日：2003-12-18

Applicant: Steven K. Sullivan ,  Raymond L. Veith ,  Iwao Akiyama ,  Yasumasa Fujisawa ,  Yukio Aizawa

Inventor： Steven K. Sullivan ,  Raymond L. Veith ,  Iwao Akiyama ,  Yasumasa Fujisawa ,  Yukio Aizawa

IPC: G06F1/02

CPC classification number: G06F1/0328

Abstract: A triggered DDS generator architecture accumulates a phase increment value in response to a DDS clock to generate phase accumulator values for addressing a waveform lookup table which contains a desired output signal. A time measurement circuit determines a time interval between the arrival of a trigger signal and a subsequent cycle of the DDS clock, which time interval is used to either adjust an initial phase accumulator value or delay the DDS clock so that a constant time is maintained between the arrival of the trigger signal and the desired output signal.

Abstract translation: 触发的DDS发生器结构响应于DDS时钟积累相位增量值，以产生用于寻址包含期望输出信号的波形查找表的相位累加器值。 时间测量电路确定触发信号的到达和DDS时钟的后续周期之间的时间间隔，该时间间隔用于调整初始相位累加器值或延迟DDS时钟，使得保持恒定时间在 触发信号的到达和所需的输出信号。

公开(公告)号：US07103622B1

公开(公告)日：2006-09-05

申请号：US10266410

申请日：2002-10-08

Applicant: Hans Tucholski

Inventor： Hans Tucholski

IPC: G06F1/02

CPC classification number: G06F1/0328

Abstract: A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state. The apparatus further includes means for performing an interpolation, for each DDS accumulator state having a defined transition-state, based upon the value of the preceding DDS accumulator state, means for selecting an element of the set of phase-shifted clock signals based upon the interpolation, and means for repositioning the MSB using the selected element of the phase-shifted clock signals.

Abstract translation: 一种用于减少直接数字合成器（DDS）输出中不需要的谐波的方法和装置。 该方法包括以下步骤：提供一组k个相移时钟信号，连续检查每个DDS累加器状态，以及确定DDS累加器状态是否具有定义的转换状态。 对于具有定义的转换状态的每个DDS累加器状态，基于先前的DDS累加器状态的值来执行内插，基于插值选择该组相移时钟信号的元素，并且最高有效位 （MSB）使用所选择的相移时钟信号的元件重新定位。 该装置包括用于提供一组k个相移时钟信号的装置，用于连续检查每个DDS累加器状态的装置，以及用于确定DDS累加器状态是否具有定义的转换状态的装置。 该装置还包括：用于根据先前的DDS累加器状态的值对具有定义的转换状态的每个DDS累加器状态执行内插的装置，用于基于该相移时钟信号的一组相移时钟信号的元素选择 插值和用于使用所选择的相移时钟信号的元素重新定位MSB的装置。

公开(公告)号：US20060165203A1

公开(公告)日：2006-07-27

申请号：US10548115

申请日：2004-02-12

Applicant: Neil Thomas ,  Peter Howlett Fox

Inventor： Neil Thomas ,  Peter Howlett Fox

IPC: H04L7/00

CPC classification number: G06F1/0328

Abstract: A waveform generator for generating a smooth version of an original waveform which contains abrupt transitions, includes a phase accumulator incremented at successive sampling times to produce an output representative of the phase of the original waveform, a phase scaler arranged to convert the residual contents of the accumulator following a transition from phase to time, computing means responsive to the time to calculate a number of samples along a smooth transition, each offset by that time from the sampling times, and a sequencer to replace the otherwise abrupt transition with the sequence of samples from the computed smooth transition.

Abstract translation: 用于产生包含突变的原始波形的平滑版本的波形发生器包括在连续采样时间递增的相位累加器，以产生代表原始波形的相位的输出;相位定标器，被布置成将 累加器在相对于时间的转变之后，响应于时间来计算沿着平滑过渡的每个样本的时间的计算装置，每个样本从采样时间偏移到该时间，以及定序器以用样本序列代替另外的突变过渡 从计算的平滑过渡。

公开(公告)号：US20060139102A1

公开(公告)日：2006-06-29

申请号：US11297003

申请日：2005-12-08

Applicant: Hans Tucholski

Inventor： Hans Tucholski

IPC: H03L7/085

CPC classification number: G06F1/08 ,  G06F1/0328 ,  H03L7/16

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced. The data processing circuit (25) reads the mode of operation and the frequency domain data and if appropriate the time domain data of a frequency swept synthesised output signal to be produced by the digital frequency synthesiser (1) from the data storing circuit (12), and computes the values of the frequency control digital word and the sequence in which the values of the frequency control digital word are to be applied to the direct digital synthesiser (5). Depending on the mode of operation, the data processing circuit (25) determines the rate at which the values of the frequency control digital word are to be applied to the direct digital synthesiser (5) in response to a logic control signal applied to a control terminal (20) or as a function of a number of clock cycles of a system clock signal applied on a system clock terminal (10) or a number of cycles of the frequency swept synthesised output signal. The frequency swept synthesised output signal may also be produced in frequency bursts.

Abstract translation: 用于合成可选择频率扫描的频率扫描合成输出信号的单芯片数字频率合成器（1）包括直接数字合成器（5），其在输出端子（7）上产生频率扫描合成输出信号，响应于 由片上数据处理电路（25）施加到频率控制输入（8）的频率控制数字字。 片上可编程数据存储电路（12）可编程为存储指示数字频率合成器（1）将要工作的选定模式的数据，并存储表示频率扫描的可选择频率和时域的数据 合成输出信号。 数据处理电路（25）从数据存储电路（12）读取数字频率合成器（1）产生的频率扫描合成输出信号的时域数据和频域数据，如果合适的话， ，并且计算频率控制数字字的值和将频率控制数字字的值应用于直接数字合成器（5）的序列。 根据操作模式，数据处理电路（25）响应于施加到控制器的逻辑控制信号来确定将频率控制数字字的值应用于直接数字合成器（5）的速率 终端（20）或者作为施加在系统时钟端（10）上的系统时钟信号的时钟周期数或频率合成输出信号的周期数的函数。 频率扫描合成输出信号也可以在频率脉冲串中产生。

公开(公告)号：US07064616B2

公开(公告)日：2006-06-20

申请号：US10748488

申请日：2003-12-29

Applicant: Peter Reichert

Inventor： Peter Reichert

IPC: H03L7/00

CPC classification number: G06F1/0328

Abstract: A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.

Abstract translation: 公开了一种数字计数器振荡器，其包括商累加器和余数累加器。 商累加器具有用于接收QUOTIENT值的可编程输入，参考时钟输入和多位输出。 该输出适于发送表示累积商数的输出值OUT。 响应于每个参考时钟周期，多位输出增加预定量。 剩余累加器包括可编程输入，用于接收相应的REMAINDER和DIVISOR值，参考时钟输入和表示累积的数字余数和小于预定数字整数的多位输出。 剩余累加器还包括具有用于接收编程除数值的第一输入的比较器和用于接收余数累加器多位输出的第二输入。 当余数多位输出达到预定义的整数值时，比较器可操作以产生用于应用于商积累器的递增进位信号。

公开(公告)号：US06922089B2

公开(公告)日：2005-07-26

申请号：US10655898

申请日：2003-09-04

Applicant: David Shiung

Inventor： David Shiung

IPC: G06F1/03 ,  H03B21/00 ,  H03K7/00

CPC classification number: G06F1/0328

Abstract: The present invention provides an all-digital frequency synthesizer circuit using interpolation technique and Linear Feedback Shift Register (LFSR). This synthesizer adaptively outputs two sequences stored in a bank of memory, or shift register. Using the idea of interpolation, all synthesizable frequencies located between two predetermined threshold frequencies can be obtained, and resolution is determined by the order of LFSR thereby. A frequency synthesizing system is also included in the present invention.

Abstract translation: 本发明提供一种使用内插技术和线性反馈移位寄存器（LFSR）的全数字频率合成器电路。 该合成器自适应地输出存储在一组存储器或移位寄存器中的两个序列。 使用插值的思想，可以获得位于两个预定阈值频率之间的所有可合成频率，并且通过LFSR的顺序来确定分辨率。 频率合成系统也包括在本发明中。

公开(公告)号：US20050135524A1

公开(公告)日：2005-06-23

申请号：US10744037

申请日：2003-12-23

Applicant: Jason Messier

Inventor： Jason Messier

IPC: G01R31/3183 ,  G06F1/02 ,  G06F1/03 ,  H04L7/00

CPC classification number: G06F1/0328 ,  G06F1/08

Abstract: An automatic test system using a DDS signal generator to create a signal with high spectral purity or a low jitter digital clock. The low jitter clock has variable frequency and is programmed to control other test functions, such as the generation of arbitrary waveforms. The DDS uses a high resolution, high sampling rate DAC to generate a sine wave that is converted to a digital clock. The architecture of the DDS signal generator allows low cost CMOS circuitry to be used to generate the data stream that feeds the high sample rate DAC.

Abstract translation: 使用DDS信号发生器创建具有高光谱纯度的信号或低抖动数字时钟的自动测试系统。 低抖动时钟具有可变频率，并被编程为控制其他测试功能，例如产生任意波形。 DDS使用高分辨率，高采样率DAC来产生转换为数字时钟的正弦波。 DDS信号发生器的架构允许使用低成本CMOS电路来产生馈送高采样率DAC的数据流。

公开(公告)号：US06650150B2

公开(公告)日：2003-11-18

申请号：US09988276

申请日：2001-11-19

Applicant: Pierre-André Farine ,  Jean-Daniel Etienne ,  Ruud Riem-Vis ,  Elham Firouzi

Inventor： Pierre-André Farine ,  Jean-Daniel Etienne ,  Ruud Riem-Vis ,  Elham Firouzi

IPC: H03B2100

CPC classification number: G06F7/68 ,  G01S19/13 ,  G01S19/29 ,  G01S19/34 ,  G01S19/35 ,  G06F1/0328 ,  H04B2001/70706

Abstract: The numerically controlled oscillator (8) is mounted in particular in a radiofrequency signal receiver which further includes means (3) for receiving and shaping the radiofrequency signals, a correlation stage (4) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage (12) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage (12) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency. Output bits (Qb) or binary signals from the second stage are multiplied by N to be introduced at the input of the first stage every N cycles of the clock signal at the first frequency (CLK).