公开(公告)号：US3863248A

公开(公告)日：1975-01-28

申请号：US32056573

申请日：1973-01-02

申请人： UNIV SHERBROOKE

发明人： DESCHENES PIERRE A ,  STEPHENNE HUBERT ,  VILLERET MICHEL

IPC分类号： H03G7/00 ,  H03M7/50 ,  H03K13/00

CPC分类号： H03M7/50 ,  H03G7/007

摘要： A compressor-expander for converting m digit coded signals into n digit coded signals according to a desired input-output continuous characteristic. The compressor comprises first means for converting the m digit coded signals into p digit coded signals, p

摘要翻译： 一种用于根据期望的输入 - 输出连续特性将m位编码信号转换成n位编码信号的压缩器 - 扩展器。 压缩机包括用于将m位编码信号转换成p位编码信号p

公开(公告)号：US3789392A

公开(公告)日：1974-01-29

申请号：US3789392D

申请日：1971-09-02

申请人： SITS SOC IT TELECOM SIEMENS

发明人： CANDIANI G

IPC分类号： H03M7/50

CPC分类号： H03M7/50

摘要： A 12-bit word, including a polarity of sign bit Qs and up to seven initial zeroes preceding a group of significant bits, is converted into a compressed eight-bit word which retains the sign bit Qs in first position and four significant bits X, Y, Z, W in the last positions; the intervening three bits are the binary equivalent of the number of initial zeroes. These intervening bits are generated by a three-stage reverse counter which is loaded by a starting pulse after arrival of the sign bit and is stepped by successive clock pulses, stopping after seven cycles at the count 0 unless cut off earlier by the arrival of the first ''''one'''' following the sign bit in the original word. This first ''''one'''', or a timing pulse occurring seven cycles after the starting pulse, initiates the stepping of a shift register in which the bits X, Y, Z, W are entered for subsequent transfer to a synthesizing register also receiving the sign bit Qs and the reading of the reverse counter.

摘要翻译： 包括符号位Qs的极性和有效位组之前的最多七个初始零的12位字被转换成将符号位Qs保持在第一位置和四个有效位X的压缩八位字， Y，Z，W在最后的位置; 中间的三位是初始值的二进制数。 这些中间位由三级反向计数器产生，三位反向计数器在符号位到达之后由起始脉冲加载，并由连续的时钟脉冲进行步进，在计数0之后停止七个周期，除非由于到达 第一个“一”跟随原始字中的符号位。 这个第一个“一个”或在起始脉冲之后七个周期发生的定时脉冲启动移位寄存器的步进，其中输入位X，Y，Z，W，以便随后传送到也接收符号位的合成寄存器 Qs和反向计数器的读数。

公开(公告)号：US3755808A

公开(公告)日：1973-08-28

申请号：US3755808D

申请日：1971-09-02

申请人： SITS SOC IT TELECOM SIEMENS

发明人： CANDIANI G

IPC分类号： H03M7/50 ,  H04L3/00

CPC分类号： H03M7/50

摘要： A compressed eight-bit word, including a polarity or sign bit Qs, three range-indicating bits a, b, c and a group of four significant bits X, Y, Z, W, is reconverted into an original 12bit word by introducing (7 - n) zeroes between the sign bit Qs and the significant group, with n representing the numerical value of the three-bit combination a, b, c, inserting a 1 just ahead of bit X unless a b c 0, and adding a 1 (followed only by ''''0''s'''') immediately behind bit W if this bit is in other than the No. 12 position. A logic matrix, forming part of a range decoder, receives the bits a, b, c from an eight-stage input register to control the transfer of significant bits X, U, Z, W to consecutive stages of a 12-bit expansion register, along with an immediately preceding 1 if any of the controlling bits has a finite value. This group of bits is followed in the expansion register by at least one 1 whose position determines the extent to which the significant group with its leading 1 must be shifted away from the sign bit Qs invariably tranferred to the first stage of that register.

摘要翻译： 包括极性或符号位Qs，三个范围指示位a，b，c和一组四个有效位X，Y，Z，W的压缩八位字被重新转换为原始的12位字，由 在符号位Qs和有效组之间引入（7-n）个零，其中n表示三位组合a，b，c的数值，在位X之前插入1，除非a = b = c = 0，如果该位不在12号位置，则在位W之后立即添加1（后跟“0”）。 形成范围解码器的一部分的逻辑矩阵从八级输入寄存器接收位a，b，c，以控制有效位X，U，Z，W到12位扩展寄存器的连续级的传输 ，以及紧接在前的1，如果任何控制位具有有限值。 该扩展寄存器中的这一组位在至少一个1之后，其位置决定了其前导1的重要组必须从标志位Qs移开的程度总是转移到该寄存器的第一阶段。

公开(公告)号：US3752970A

公开(公告)日：1973-08-14

申请号：US3752970D

申请日：1971-12-22

申请人： BELL TELEPHONE LABOR INC

发明人： AARON M ,  KANEKO H

IPC分类号： H03G3/00 ,  H03G7/00 ,  H03H17/00 ,  H03M7/00 ,  H03M7/50 ,  H04B14/02 ,  H04B14/04 ,  G06F7/39

CPC分类号： H04B14/048 ,  H03G3/002 ,  H03G7/007 ,  H03H17/0054 ,  H03M7/50 ,  H04B14/02

摘要： Attenuation is performed directly on a compressed PCM code by means of a circuit which treats the characteristic bits and the mantissa bits in accordance with an attenuation algorithm. The characteristic bits are applied to a counter circuit whose output is used to produce a first term of the algorithm and the mantissa bits are applied to a shift register whose output is used to generate a second term of the algorithm. The two terms are added together and used to generate the characteristic bits of the attenuated signal.

摘要翻译： 衰减通过根据衰减算法处理特征位和尾数位的电路在压缩PCM码上直接执行。 特征位被应用于计数器电路，其输出用于产生算法的第一项，并且尾数位被施加到移位寄存器，该移位寄存器的输出用于产生该算法的第二项。 将这两个项相加在一起，并用于产生衰减信号的特征位。