公开(公告)号：US09843802B1

公开(公告)日：2017-12-12

申请号：US13436641

申请日：2012-03-30

申请人： Grant R. Wallace ,  Philip N. Shilane ,  Frederick Douglis ,  Jianqiang Luo

发明人： Grant R. Wallace ,  Philip N. Shilane ,  Frederick Douglis ,  Jianqiang Luo

IPC分类号： G06K9/36 ,  H04N19/10 ,  H04L12/811

CPC分类号： H04N19/10 ,  H03M7/30 ,  H03M7/50 ,  H03M7/607 ,  H04L47/38

摘要： A computer-implemented method for compressing a data set, the method comprising receiving a first data block of the data set, selecting automatically by a compression management module a compression module from a plurality of compression modules to apply to the first data block based on projected compression efficacy or resource utilization, and compressing the first data block with the selected compression module to generate a first compressed data block.

公开(公告)号：US20110158328A1

公开(公告)日：2011-06-30

申请号：US13061971

申请日：2009-10-07

申请人： Noboru Harada ,  Yutaka Kamamoto ,  Takehiro Moriya

发明人： Noboru Harada ,  Yutaka Kamamoto ,  Takehiro Moriya

IPC分类号： H04L27/00 ,  H04B14/04

CPC分类号： H03M7/50 ,  G10L19/0017

摘要： A frame formed of a plurality of code words encoded with an encoding mode in which two different types of code words are assigned one-to-one to two smallest quantization intervals is checked to determine whether it contains just the two types of code words assigned to the two smallest quantization intervals, and lossless encoding is applied to the frame containing just the two types of code words. A code obtained by this lossless encoding is decoded with a decoding method corresponding to the lossless encoding.

摘要翻译： 检查由多个编码模式形成的帧，其中两种不同类型的码字分配一对一到两个最小量化间隔的编码模式，以确定它是否仅包含分配给 将两个最小的量化间隔和无损编码应用于仅包含两种类型的码字的帧。 通过该无损编码获得的代码用对应于无损编码的解码方法解码。

公开(公告)号：US20040261120A1

公开(公告)日：2004-12-23

申请号：US10465326

申请日：2003-06-18

申请人： General Instrument Corporation

发明人： Mao Zhu Zhang ,  Robert L. Howald

IPC分类号： H04N007/173 ,  H04N007/16

CPC分类号： H03M7/50 ,  H03M7/30 ,  H04N7/17309 ,  H04N7/22 ,  H04N21/6168

摘要： In a cable return path system, a method for performing digital companding adds a predetermined offset to the digital value to be companded, and employs a modified null-law or a-law companding technique to obtain a reduced bit length digital value. One embodiment of this modified approach adds a predetermined offset (e.g., 129 for a 12-bit implementation) to the digital value before companding and then employs a two-bit chord and a 5-bit step for the 12-bit implementation. The end result is that the performance metrics are not significantly compromised by this bit reduction when compared to current transmission methods without this technique.

摘要翻译： 在电缆返回路径系统中，用于执行数字压扩的方法对要压缩的数字值添加预定的偏移量，并且采用修正的mu律或法则压扩技术来获得缩减的位长数字值。 该修改的方法的一个实施例在压扩之前将预定偏移（例如，用于12位实现的129）添加到数字值，然后对于12位实现采用两位和弦和5位步。 最终的结果是，与没有这种技术的当前传输方法相比，性能度量不会被这个比特减少显着地损害。

公开(公告)号：US06317063B1

公开(公告)日：2001-11-13

申请号：US09523925

申请日：2000-03-09

申请人： Katsushige Matsubara

发明人： Katsushige Matsubara

IPC分类号： H03M740

CPC分类号： H03M7/50 ,  H03M7/42

摘要： In an inversely quantizing method of determining an inverse quantization value Y from an original quantization index value X, scale conversion is performed to a quantization index value X1 as at least a part of the original quantization index value X to produce first and second values which indicate the quantization index value X1. Then, first and second tables are referred to based on the first and second values, to determine third and fourth values corresponding to the first and second values, respectively. Then, an inverse quantization value Y is determined from the third and fourth values.

摘要翻译： 在从原始量化索引值X确定逆量化值Y的逆量化方法中，对作为原始量化索引值X的至少一部分的量化索引值X1进行缩放转换，以产生指示 量化指标值X1。 然后，基于第一和第二值参考第一和第二表，以分别确定对应于第一和第二值的第三和第四值。 然后，从第三和第四值确定反量化值Y.

公开(公告)号：US06198940B1

公开(公告)日：2001-03-06

申请号：US09105467

申请日：1998-06-26

申请人： Kouichi Matsumoto

发明人： Kouichi Matsumoto

IPC分类号： H04Q720

CPC分类号： H03M7/50

摘要： A mobile radiophone apparatus includes an A/D converter for outputting an input analogue voice signal as quantized data and a highly efficient voice encoder for extracting features of the quantized data output from the A/D converter and converting the data to codes of a smaller quantity by a fixed time unit. The number of quantization bits in the A/D converter is established to be larger than the number of quantization bits possible to be input to the highly efficient voice encoder. A bit-number converter is provided for converting the number of bits of the quantized data output at the A/D converter to the number of quantization bits possible to be input to the highly efficient voice encoder corresponding to a maximum amplitude value within the fixed time unit. the conversion parameter for the quantized data in the bit-number converter is transmitted in addition to the codes output at the highly efficient voice encoder.

摘要翻译： 一种移动无线电电话设备包括用于输出作为量化数据的输入模拟语音信号的A / D转换器和用于提取从A / D转换器输出的量化数据的特征的高效语音编码器，并将该数据转换成较小量的代码 以固定的时间单位。 A / D转换器中的量化比特数被建立为比可能输入到高效语音编码器的量化比特数量大。 提供了一个位数转换器，用于将在A / D转换器输出的量化数据的位数转换为可能输入到与固定时间内的最大幅度值相对应的高效语音编码器的量化位数 单元。 除了在高效语音编码器输出的代码之外，还发送比特数转换器中的量化数据的转换参数。

公开(公告)号：US5941939A

公开(公告)日：1999-08-24

申请号：US881903

申请日：1997-06-25

申请人： Shao Wei Pan ,  Shay-Ping Thomas Wang

发明人： Shao Wei Pan ,  Shay-Ping Thomas Wang

IPC分类号： G06F1/035 ,  H03M7/50 ,  G06F7/00

CPC分类号： H03M7/50 ,  G06F1/0356 ,  G06F2101/10

摘要： A converter, which may be used for implementing either logarithmic or inverse-logarithmic functions, includes a memory, a multiplier, and an adder. The memory stores a plurality of parameters which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values.

摘要翻译： A转换器，其可以被用于实现任一对数或反对数函数，包括存储器，乘法器和加法器。 所述存储器存储多个被使用最小二乘法来估计在输入值的域的对数或反对数函数导出的参数。

公开(公告)号：US5604691A

公开(公告)日：1997-02-18

申请号：US381167

申请日：1995-01-31

申请人： James D. Dworkin ,  John M. Buss

发明人： James D. Dworkin ,  John M. Buss

IPC分类号： G06F1/03 ,  G06F7/556 ,  H03M7/50 ,  G06F7/00 ,  G06F1/02 ,  G06F15/00

CPC分类号： G06F7/556 ,  G06F1/0307 ,  H03M7/50

摘要： A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, two multiplier, and two adders. The memory stores a plurality of coefficient which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

摘要翻译： 公开了可用于实现对数或反对数函数的转换器。 该转换器包括一个存储器，两个乘法器和两个加法器。 存储器存储基于用于估计输入值的域上的对数或反对数函数的二阶泰勒多项式的多个系数。 还公开了一种使用该转​​换器的方法。

公开(公告)号：US5212481A

公开(公告)日：1993-05-18

申请号：US649592

申请日：1991-02-01

申请人： Masaki Ichihara

发明人： Masaki Ichihara

IPC分类号： G06F7/556 ,  H03M7/50

CPC分类号： G06F7/556 ,  H03M7/50

摘要： A circuit for converting a 8-bit .mu.LawPCM code into a 14-bit linear code comprising an inversion circuit receiving a 8-bit .mu.LawPCM code for outputting a 8-bit inverted signal. A 6-bit signal is obtained by putting a bit of "1" at a place lower than the least significant bit of less significant four bits of the 8-bit inverted signal by one bit and another bit of "1" at a place higher than the most significant bit of the less significant four bits of the 8-bit inverted signal by one bit. The 6-bit signal is shifted by a bit shift circuit in the most significant bit direction by the amount which is within a range of 0 bit to 7 bits and which is determined by second to fourth significant bits of the 8-bit inverted signal. The result of shift in the form of 13-bit signal outputted from the bit shift circuit is added with a predetermined number by a constant number addition circuit, and a 14-bit linear code is constituted of a 13-bit output of the addition circuit and the most significant bit of the 8-bit inverted signal added as a sign bit.

摘要翻译： 一种用于将8位的μLawPCM码转换成14位线性码的电路，包括一个反相电路，该反相电路接收一个用于输出8位反相信号的8位μLawPCM码。 通过在比8位反相信号的较低有效四位的最低有效位低1位的地方放置一位“1”，在更高的位置放置另一位“1”来获得6位信号 比8位反相信号的最低有效位4位低一位。 6位信号由位移位电路在最高有效位方向移位量在0比特到7比特的范围内，由8位反相信号的第二到第四有效位决定。 由位移电路输出的13位信号的移位结果通过常数加法电路加上预定数，14位线性码由加法电路的13位输出构成 并且8位反相信号的最高有效位作为符号位添加。

公开(公告)号：US4897652A

公开(公告)日：1990-01-30

申请号：US174470

申请日：1988-03-28

申请人： Remi Leon

发明人： Remi Leon

IPC分类号： G06F7/57 ,  H03M7/50

CPC分类号： H03M7/50 ,  G06F7/483

摘要： A coding method uses a pseudo-logarithmic compression law approximated by a straight line segment curve. Its code word on n+1 binary digits, where n is a positive invariant integer, has a lefthand part made up of a variable number p of binary digits having the same value (1) corresponding to the rank number of the segment concerned in the compression law and a righthand part, which may be absent, determining the interval within the segment concerned. It may be implemented on the basis of a series of counting pulses defining the number to be coded by means of a circuit which comprises a divider circuit having a plurality of division ratios operating on the series of counting pulses, a synchronization circuit which also selects the division ratio of the divider circuit corresponding to the increment between intervals in the segment concerned of the compression law, and a counting circuit operating on the series of pulses delivered by the divider circuit and supplying on parallel outputs the value of the code word corresponding to the number of counting pulses applied to the input of the divider circuit.

摘要翻译： 编码方法使用由直线段曲线近似的伪对数压缩定律。 其n + 1个二进制数字上的代码字，其中n是正不变整数，具有一个左边部分，该部分由具有相同值（1）的二进制数字的可变数p构成，该值对应于 压缩法和右手部分，可能不存在，确定相关段内的间隔。 它可以基于一系列计数脉冲来实现，这些计数脉冲通过包括在一系列计数脉冲上具有多个分频比的分频电路的电路来定义要被编码的数字，同步电路还选择 对应于与压缩规律有关的段中的间隔之间的增量的分频器电路的分频比，以及对由分频器电路传送的一系列脉冲进行操作并对并行输出提供的代码字的值的计数电路， 施加到除法器电路的输入的计数脉冲数。

公开(公告)号：US4500869A

公开(公告)日：1985-02-19

申请号：US178531

申请日：1980-08-15

申请人： Rolf Zeitraeg

发明人： Rolf Zeitraeg

IPC分类号： H03G7/00 ,  H03M7/50 ,  H04B1/64 ,  H04B14/04 ,  H03K13/24

CPC分类号： H03M7/50 ,  H03G7/007

摘要： A technique for converting linearly encoded digital signals into non-linearly encoded digital signals using two separate ROMs.

摘要翻译： 一种使用两个单独的ROM将线性编码的数字信号转换为非线性编码的数字信号的技术。