公开(公告)号：US20100202183A1

公开(公告)日：2010-08-12

申请号：US12701140

申请日：2010-02-05

申请人： Wlodek KURJANOWICZ

发明人： Wlodek KURJANOWICZ

IPC分类号： G11C17/00 ,  G11C8/08 ,  G11C7/02

CPC分类号： G11C17/16 ,  G11C16/22 ,  G11C17/18

摘要： A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.

摘要翻译： 一种用于通过将至少两个OTP存储单元中存储一位数据来提高OTP存储器，特别是反熔丝存储器的可靠性的方法和系统。 因此，通过以多单元每位模式同时访问至少两个OTP存储单元来读出数据的每一位。 通过将至少两个OTP存储器单元中的一位数据存储，补偿缺陷单元或弱可编程单元，因为附加单元或单元提供固有冗余。 程序的可靠性通过一次编程数据一个位来确保，并且在正常操作之前验证所有编程的位，在正常操作之前，以多单元每位模式读出数据。 使用用于反熔丝存储器的新型程序/验证算法，以高速度和最小功耗实现编程和验证。 除了改进的可靠性，读取容限和读取速度都比单个单元每位存储器改进。

公开(公告)号：US20100188881A1

公开(公告)日：2010-07-29

申请号：US12666771

申请日：2009-05-25

申请人： Zaisheng He ,  Moutao Li ,  Lirong Xiao

发明人： Zaisheng He ,  Moutao Li ,  Lirong Xiao

IPC分类号： G11C17/16 ,  G11C17/00

CPC分类号： G01R31/318511

摘要： The present invention discloses a method for adjusting a reference voltage, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation value between the two; configuring an adjustment code according to the deviation value; and, burning the adjustment code into a nonvolatile storage medium. The present invention also discloses an apparatus for adjusting a reference voltage. According to the method and apparatus for adjusting a reference voltage provided by embodiments of the present invention, the reference voltage need not be adjusted according to an external power supply's different application schemes. Thus, adjustment on the reference voltage of the chip is standardized and costs of the chip's application schemes are saved. Embodiments of the present invention further provide a method and apparatus for obtaining a reference voltage, which makes it not necessary to configure a dedicated reference voltage pin in the chip for introducing an external reference voltage, and thus stability of the circuit's working is improved and costs of the chip's applications are decreased.

摘要翻译： 本发明公开了一种用于调整参考电压的方法，包括：对配置在芯片中的参考电压寄存器中的默认代码进行解码以获得实际参考电压; 将实际参考电压与基准值进行比较，以获得两者之间的偏差值; 根据偏差值配置调整码; 并且将调整代码刻录到非易失性存储介质中。 本发明还公开了一种用于调整参考电压的装置。 根据本发明实施例提供的用于调整参考电压的方法和装置，不需要根据外部电源的不同应用方案来调整参考电压。 因此，对芯片的参考电压进行调整是标准化的，并节省了芯片的应用方案的成本。 本发明的实施例还提供了一种用于获得参考电压的方法和装置，这使得不需要在芯片中配置用于引入外部参考电压的专用参考电压引脚，从而提高了电路工作的稳定性和成本 的芯片应用减少了。

公开(公告)号：US20100188880A1

公开(公告)日：2010-07-29

申请号：US12473387

申请日：2009-05-28

申请人： Barry STAKELY

发明人： Barry STAKELY

IPC分类号： G11C17/00 ,  G11C5/14 ,  G05F1/10

CPC分类号： G11C17/18 ,  G11C5/145 ,  G11C29/02 ,  G11C29/021 ,  G11C2029/0409

摘要： A voltage generation and power switching apparatus, method and system is described. The apparatus includes a digital media processing chip. The digital media processing chip includes a control unit, a one-time programmable memory, a charge pump and a switching network. The control unit is to receive an operating state. The charge pump is connected to a first voltage and configured to generate a second voltage using the first voltage. The control unit activates the charge pump based upon the received operating state. The one-time programmable memory is connected to the charge pump via a switching network. The switching network is configured by the control unit to provide a voltage required by the received operating state to the one-time programmable memory.

摘要翻译： 描述了电压产生和电力开关装置，方法和系统。 该装置包括数字媒体处理芯片。 数字媒体处理芯片包括控制单元，一次可编程存储器，电荷泵和交换网络。 控制单元将接收操作状态。 电荷泵连接到第一电压并被配置为使用第一电压产生第二电压。 控制单元基于所接收的操作状态激活电荷泵。 一次性可编程存储器通过交换网络连接到电荷泵。 交换网络由控制单元配置，以将接收的操作状态所需的电压提供给一次性可编程存储器。

公开(公告)号：US07760553B2

公开(公告)日：2010-07-20

申请号：US12016782

申请日：2008-01-18

申请人： Chae Kyu Jang

发明人： Chae Kyu Jang

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C17/00 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/785

摘要： A fuse circuit in a flash memory device is disclosed. The fuse circuit includes a plurality of memory cells turned on/off by a first voltage in accordance with program state, a switching circuit configured to switch in response to a control signal, thereby transmitting a verifying signal for verifying program of the memory cell to the memory cell, and a cell controller configured to output the verifying signal for controlling program, verification and erase of the memory cells and the control signal.

摘要翻译： 公开了一种闪存器件中的熔丝电路。 熔丝电路包括根据编程状态由第一电压导通/关断的多个存储器单元，切换电路被配置为响应于控制信号进行切换，从而将用于验证存储器单元的程序的验证信号发送到 存储单元和单元控制器，其被配置为输出用于控制存储单元的控制程序，验证和擦除以及控制信号的验证信号。

公开(公告)号：US20100177548A1

公开(公告)日：2010-07-15

申请号：US12634166

申请日：2009-12-09

申请人： Dong-ki MIN ,  Hoo-sang OH

发明人： Dong-ki MIN ,  Hoo-sang OH

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： G11C11/5692 ,  G11C17/16

摘要： A multilevel one-time programmable memory device includes a plurality of memory cells, wherein each of the plurality of memory cells includes: a first electrode to which a first voltage is applied, a second electrode to which a second voltage is applied and a plurality of fuse lines performing a fusing operation according to a voltage difference between the first electrode and the second electrode. The plurality of fuse lines are connected to each other between the first electrode and the second electrode. In addition, at least one of the first electrode and the second electrode is formed such that the first electrode and the second electrode have different valid line lengths from each other therebetween so that the plurality of fuse lines have different resistances from each other.

摘要翻译： 多级一次可编程存储器件包括多个存储器单元，其中多个存储器单元中的每一个包括：施加第一电压的第一电极，施加第二电压的第二电极， 熔丝线根据第一电极和第二电极之间的电压差来执行定影操作。 多个熔丝线在第一电极和第二电极之间彼此连接。 此外，第一电极和第二电极中的至少一个形成为使得第一电极和第二电极之间的有效线长度彼此不同，使得多个熔丝线彼此具有不同的电阻。

公开(公告)号：US07751225B2

公开(公告)日：2010-07-06

申请号：US12016726

申请日：2008-01-18

申请人： Gil I. Winograd ,  Morteza Cyrus Afghahi ,  Esin Terzioglu

发明人： Gil I. Winograd ,  Morteza Cyrus Afghahi ,  Esin Terzioglu

IPC分类号： G11C17/00

CPC分类号： G11C17/10 ,  H01L27/112 ,  H01L27/11226

摘要： In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.

摘要翻译： 在一个实施例中，提供了只读存储器（ROM），其包括：多个字线; 多个位线; 多个存储单元晶体管，其布置成与字线对应的行，使得如果字线被断言，相应的存储单元晶体管正在导通，则存储单元晶体管也被布置在与位线对应的列中; 其中每列存储单元晶体管被布置成列组，每个列组包括耦合到对应位线的存取晶体管，列组中的剩余晶体管从存取晶体管串联耦合到列组中的最后一个晶体管 列组中的最后一个晶体管耦合到电压节点。

公开(公告)号：US20100165698A1

公开(公告)日：2010-07-01

申请号：US12650238

申请日：2009-12-30

申请人： David K.Y. Liu

发明人： David K.Y. Liu

IPC分类号： G11C17/00 ,  H03K19/177

CPC分类号： H03K19/0002 ,  G11C16/0441 ,  G11C17/14 ,  G11C2216/10 ,  G11C2216/26 ,  H01L27/11521 ,  H01L27/11558 ,  H01L27/11803 ,  H01L29/7885 ,  H03K19/177

摘要： A programmable non-volatile configuration circuit uses a pair of non-volatile memory devices arranged in a pull-up and pull-down arrangement. The non-volatile memory devices have floating gates that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments to store configuration data for programmable logic devices, field programmable arrays, and many other applications.

摘要翻译： 可编程非易失性配置电路使用以上拉和下拉布置布置的一对非易失性存储器件。 非易失性存储器件具有与源极/漏极区域的可变部分重叠的浮动栅极。 这允许通过可变电容耦合将器件的编程电压赋予浮置栅极，从而改变器件的状态。 本发明可用于存储用于可编程逻辑器件，现场可编程阵列和许多其它应用的配置数据的环境中。

公开(公告)号：US20100157648A1

公开(公告)日：2010-06-24

申请号：US12555031

申请日：2009-09-08

申请人： Tomohiro Kobayashi

发明人： Tomohiro Kobayashi

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C8/18

CPC分类号： G11C17/16 ,  G11C17/165 ,  G11C17/18

摘要： A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions.

摘要翻译： 半导体集成电路器件包括第一块，第二块和控制部。 第一块包括第一熔丝，被配置为向第一熔丝写入数据的第一转换器，能够保持第一指令的第一保持部分和被配置为当给予第二指令时接通第一切换的第一指令部分 用第一个指令。 第二块包括第二熔丝，第二开关被配置为向第二熔丝写入数据，第二保持部分能够保持第一指令;以及第二指令部分，配置成当给予第二指令时接通第二切换 用第一个指令。 控制部分在第一指令被保持在第一和第二保持部分的时间点发出第二指令。

公开(公告)号：US20100128511A1

公开(公告)日：2010-05-27

申请号：US12319573

申请日：2009-01-09

申请人： Eugene Robert Worley

发明人： Eugene Robert Worley

IPC分类号： G11C17/00 ,  G11C17/06 ,  G11C7/06

CPC分类号： G11C17/18 ,  G11C17/16 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention shows how diodes in a modern semiconductor process can be used as a very compact switch element in a Programmable Read Only Memory (PROM) using common integrated circuit fuse elements such as polysilicon and metal. This compact switch element allows very dense PROM arrays to be realized since diodes have the highest conduction density of any semiconductor device. The high conduction density is used to provide the relatively high current needed to blow the fuse element open. Since MOSFETs are typically used as fuse array switch elements, a relatively large area is required for the MOSFET to reach the current needed to blow the fuse element. Since diodes are two terminal switch elements unlike MOSFETs which are three terminal devices, methods are outlined on how to both read and write the arrays using this two terminal switch.

摘要翻译： 本发明示出了现代半导体工艺中的二极管如何可以用作可编程只读存储器（PROM）中使用诸如多晶硅和金属的公共集成电路熔丝元件的非常紧凑的开关元件。 这种紧凑的开关元件允许实现非常致密的PROM阵列，因为二极管具有任何半导体器件的最高导通密度。 高导通密度用于提供吹开保险丝元件所需的相对高的电流。 由于MOSFET通常用作熔丝阵列开关元件，MOSFET需要相对较大的面积才能达到熔断熔丝元件所需的电流。 由于二极管是不同于三端子器件的MOSFET的两个端子开关元件，所以概述了如何使用这个两个端子开关读取和写入阵列的方法。

公开(公告)号：US20100110750A1

公开(公告)日：2010-05-06

申请号：US12553616

申请日：2009-09-03

申请人： Toshimasa Namekawa

发明人： Toshimasa Namekawa

IPC分类号： G11C17/00 ,  G11C7/10 ,  G11C5/14 ,  G11C8/08

CPC分类号： G11C17/18 ,  G11C5/145 ,  G11C17/16 ,  G11C17/165 ,  H01L27/11206 ,  H01L27/115

摘要： The row decoder receives writing instruction signal and reading instruction signal to selectively activate one of the word lines according to an input state of row address signals. The data buffer receives a data input signal when the writing instruction signal is received, and drives corresponding one of the bit lines and amplifies a minute reading signal transmitted to one of the bit lines to output a data output signal when the reading instruction signal is received.The power supply circuit supplies a certain voltage to the memory cell, and in response to the reading instruction signal, keeps the voltage at a ground potential.

摘要翻译： 行解码器接收写入指令信号和读取指令信号，以根据行地址信号的输入状态选择性地激活字线之一。 当接收到写入指令信号时，数据缓冲器接收数据输入信号，并驱动对应的一个位线，并且当接收到读取指令信号时，放大发送到一个位线的分钟读取信号以输出数据输出信号 。 电源电路向存储单元提供一定的电压，并且响应于读取指令信号将电压保持在接地电位。