公开(公告)号：US20100118608A1

公开(公告)日：2010-05-13

申请号：US12614545

申请日：2009-11-09

Applicant: Seung-Hwan SONG ,  Jaehong KIM ,  Kyoung Lae CHO ,  Yong June KIM ,  Jun Jin KONG ,  Jong Han KIM

Inventor： Seung-Hwan SONG ,  Jaehong KIM ,  Kyoung Lae CHO ,  Yong June KIM ,  Jun Jin KONG ,  Jong Han KIM

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C29/00 ,  G11C2211/5634

Abstract: A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit.

Abstract translation: 公开了一种非易失性半导体存储器件及确定读取电压的相关方法。 非易失性半导体存储器件包括： 包括多个存储单元的存储单元阵列，读电压确定单元，被配置为通过将在编程操作期间获得的参考数据与在随后的读取操作期间获得的比较数据进行比较来确定最佳读取电压，并将当前读取电压改变为新的 基于比较结果的读取电压和读取电压生成单元，被配置为响应于由读取电压确定单元提供的读取电压控制信号而产生新的读取电压。

公开(公告)号：US20100020620A1

公开(公告)日：2010-01-28

申请号：US12453964

申请日：2009-05-28

Applicant: Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

Inventor： Yong June Kim ,  Kyoung Lae Cho ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC: G11C16/04 ,  G06F12/00

CPC classification number: G11C11/5628 ,  G11C7/1006

Abstract: Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

Abstract translation: 示例性实施例可以提供存储器设备和存储器数据编程方法。 根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。 存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。 存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

公开(公告)号：US20090193313A1

公开(公告)日：2009-07-30

申请号：US12149999

申请日：2008-05-12

Applicant: Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Young Hwan Lee

Inventor： Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Young Hwan Lee

IPC: H03M13/00

CPC classification number: H03M13/29 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/3738 ,  H03M13/6561

Abstract: Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders.A method of decoding a concatenated code may include: calculating a likelihood value of concatenated encoded received data; performing first decoding for the received data based on the calculated likelihood value to generate first decoded data; performing second decoding for the first decoded data to generate second decoded data; and determining whether to perform iterative decoding based on the second decoded data.According to example embodiments, it is possible to directly manage the quality of concatenated decoded data to thereby accurately determine whether to perform iterative decoding for concatenated encoded data. Also, it may be possible to quickly decode concatenated encoded received data.

Abstract translation: 提供了用于解码级联代码的装置及其方法，其可以基于相对于多个解码器的输出的似然值来提高级联代码的解码速度。 解码级联代码的方法可以包括：计算级联编码的接收数据的似然值; 基于所计算的似然值对接收到的数据执行第一解码以生成第一解码数据; 对所述第一解码数据执行第二解码以产生第二解码数据; 以及基于所述第二解码数据来确定是否执行迭代解码。 根据示例性实施例，可以直接管理级联解码数据的质量，从而准确地确定是否对级联编码数据执行迭代解码。 此外，可以快速解码连接编码的接收数据。