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101.发明申请BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 有权用于低密度奇偶校验的位交换机检查长度为16200，编码速率为2/15和64符号映射，以及使用相同的位交互方法公开(公告)号：US20160218746A1
公开(公告)日：2016-07-28
申请号：US14718013
申请日：2015-05-20
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2767 , H03M13/1165 , H03M13/255 , H03M13/2778 , H03M13/2792 , H04L1/0057 , H04L1/0071 , H04L2001/0093
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
Abstract translation: 本文公开了一种位交织器，位交织编码调制（BICM）装置和比特交织方法。 比特交织器包括第一存储器，处理器和第二存储器。 第一存储器存储长度为16200且码率为2/15的低密度奇偶校验（LDPC）码字。 处理器通过基于比特组交织LDPC码字来产生交错码字。 位组的大小对应于LDPC码字的并行因子。 第二存储器将交织的码字提供给用于64符号映射的调制器。
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102.发明申请LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME 有权低密度奇偶校验编码器的长度为64800，编码速率为2/15，低密度奇偶校验编码方法使用该编码方法公开(公告)号：US20160049957A1
公开(公告)日：2016-02-18
申请号：US14496457
申请日：2014-09-25
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/1177 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/616 , H03M13/6552 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
Abstract translation: 公开了一种低密度奇偶校验（LDPC）编码器，LDPC解码器和LDPC编码方法。 LDPC编码器包括第一存储器，第二存储器和处理器。 第一存储器存储长度为64800，码率为2/15的LDPC码字。 第二存储器被初始化为0.处理器通过使用与奇偶校验矩阵（PCM）相对应的序列执行相对于第二存储器的累积来生成与信息位对应的LDPC码字。
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公开(公告)号：US20240171197A1
公开(公告)日：2024-05-23
申请号：US18429127
申请日：2024-01-31
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2757 , H03M13/1102 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778 , H03M13/2792 , H03M13/616 , H03M13/6552 , H04L1/0041 , H04L1/0057 , H04L1/0058 , H04L1/0071 , H04L27/20 , H04L27/3416
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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104.发明公开公开(公告)号：US20230246897A1
公开(公告)日：2023-08-03
申请号：US18298498
申请日：2023-04-11
Inventor： Sung-Ik PARK , Jae-Young LEE , Sun-Hyoung KWON , Heung-Mook KIM
IPC: H04L27/26 , H04J11/00 , H04L1/00 , H04L7/08 , H04L65/611
CPC classification number: H04L27/2627 , H04J11/004 , H04L1/0041 , H04L1/0058 , H04L1/0068 , H04L1/0071 , H04L1/0072 , H04L7/08 , H04L27/26 , H04L27/2613 , H04L27/2647 , H04L65/611
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US20220394117A1
公开(公告)日：2022-12-08
申请号：US17886167
申请日：2022-08-11
Inventor： Bo-Mi LIM , Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC: H04L69/324
Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to reduce power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time-interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling start position information and size information for each of Physical Layer Pipes (PLPs). In this case, the Physical Layer Pipes include a core layer physical layer pipe corresponding to the core layer signal and an enhanced layer physical layer pipe corresponding to the enhanced layer signal.
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Patent Agency Ranking
公开(公告)号：US20220329264A1
公开(公告)日：2022-10-13
申请号：US17845614
申请日：2022-06-21
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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107.发明申请公开(公告)号：US20220200628A1
公开(公告)日：2022-06-23
申请号：US17694774
申请日：2022-03-15
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM
Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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108.发明申请公开(公告)号：US20220094585A1
公开(公告)日：2022-03-24
申请号：US17540301
申请日：2021-12-02
Inventor： Sung-Ik PARK , Jae-Young LEE , Sun-Hyoung KWON , Heung-Mook KIM
Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.
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公开(公告)号：US20220006474A1
公开(公告)日：2022-01-06
申请号：US17479763
申请日：2021-09-20
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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110.发明申请公开(公告)号：US20210367821A1
公开(公告)日：2021-11-25
申请号：US17397843
申请日：2021-08-09
Inventor： Sung-Ik PARK , Jae-Young LEE , Sun-Hyoung KWON , Nam-Ho HUR , Heung-Mook KIM
Abstract: An apparatus and method for transmitting broadcast signal to which channel bonding is applied are disclosed. The apparatus according to the present invention includes an input formatting unit configured to generate baseband packets corresponding to a plurality of packet types using data corresponding to a physical layer pipe; a stream partitioner configured to partition the baseband packets into a plurality of partitioned streams corresponding to the plurality of packet types; BICM units configured to perform error correction encoding, interleaving and modulation corresponding to the plurality of partitioned streams, respectively; and waveform generators configured to generate RF transmission signals corresponding to the plurality of partitioned streams, respectively.
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