公开(公告)号：US11930365B2

公开(公告)日：2024-03-12

申请号：US17742890

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Liuyang Yang ,  Xiruo Liu ,  Manoj Sastry ,  Marcio Juliato ,  Shabbir Ahmed ,  Christopher Gutierrez

IPC: G06F21/00 ,  G06F13/40 ,  H04W12/00 ,  H04W12/122

CPC classification number: H04W12/122 ,  G06F13/40 ,  H04W12/009

Abstract: Systems, apparatus, methods, and techniques for reporting an attack or intrusion into an in-vehicle network are provided. The attack can be broadcast to connected vehicles over a vehicle-to-vehicle network. The broadcast can include an indication of a sub-system involved in the attack and can include a request for assistance in recovering from the attack. Connected vehicles can broadcast responses over the vehicle-to-vehicle network. The responses can include indications of data related to the compromised sub-system. The vehicle can receive the responses and can use the responses to recover from the attack, such as, estimate data.

公开(公告)号：US11917053B2

公开(公告)日：2024-02-27

申请号：US17707629

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F7/503 ,  G06F9/3012 ,  H04L9/3247

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US11777707B2

公开(公告)日：2023-10-03

申请号：US17833498

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  G06F21/72 ,  G06F7/487 ,  G06F21/60 ,  G06N3/063 ,  G06N20/00 ,  G06N3/08

CPC classification number: H04L9/008 ,  G06F7/722 ,  G06N3/08 ,  H04L9/0618

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.

公开(公告)号：US11750402B2

公开(公告)日：2023-09-05

申请号：US17534158

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3247 ,  G06F9/3877 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US11722313B2

公开(公告)日：2023-08-08

申请号：US17014600

申请日：2020-09-08

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30 ,  G06N10/00

CPC classification number: H04L9/3247 ,  G06N10/00 ,  H04L9/0618 ,  H04L9/0825 ,  H04L9/0852 ,  H04L9/0877 ,  H04L9/14 ,  H04L9/3073 ,  H04L9/0836 ,  H04L9/3239

Abstract: An apparatus comprises a plurality of hardware security modules, at least a first hardware security module in the plurality of hardware security modules comprising processing circuitry to generate a first plurality of pairs of cryptographic key pairs comprising a first plurality of private keys and a first plurality of public keys, forward the first plurality of public keys to a remote computing device, receive, from the remote computing device, a first plurality of ciphertexts, wherein each ciphertext in the plurality of ciphertexts represents an encryption of a cryptographic seed with a public key selected from the plurality of public keys, receive, from a subset of hardware security modules in the plurality of hardware security modules, a subset of private keys.

公开(公告)号：US11720662B2

公开(公告)日：2023-08-08

申请号：US16994219

申请日：2020-08-14

Applicant: Intel Corporation

Inventor： Eduardo Alban ,  Shabbir Ahmed ,  Marcio Juliato ,  Christopher Gutierrez ,  Qian Wang ,  Vuk Lesi ,  Manoj Sastry

IPC: G06F21/44 ,  G06F21/85 ,  H04L12/40 ,  G06F13/20

CPC classification number: G06F21/44 ,  G06F13/20 ,  G06F21/85 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Systems, apparatuses, and methods to identify an electronic control unit transmitting a message on a communication bus, such as an in-vehicle network bus, are provided. ECUs transmit messages by manipulating voltage on conductive lines of the bus. Observation circuitry can observe voltage signals associated with the transmission at a point on the in-vehicle network bus. A distribution can be generated from densities of the voltage signals. ECUs can be identified and/or fingerprinted based on the distributions.

公开(公告)号：US20220417019A1

公开(公告)日：2022-12-29

申请号：US17356972

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Manoj Sastry

IPC: H04L9/30 ,  H04L9/14 ,  H04L9/06

Abstract: An accelerator includes polynomial multiplier circuitry including at least one modulus multiplier operating according to a mode. The at least one modulus multiplier include a multiplier to multiply two polynomial coefficients to generate a multiplication result, a power of two reducer to reduce the multiplication result to a reduced multiplication result when the mode is a power of two mode, and a prime modulus reducer to reduce the multiplication result to the reduced multiplication result when the mode is a prime modulus mode.

公开(公告)号：US20220303034A1

公开(公告)日：2022-09-22

申请号：US17829042

申请日：2022-05-31

Applicant: INTEL CORPORATION

Inventor： Vuk Lesi ,  Christopher Gutierrez ,  Manoj Sastry ,  Marcio Juliato ,  Shabbir Ahmed ,  Qian Wang

IPC: H04J3/06

Abstract: Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

公开(公告)号：US11444961B2

公开(公告)日：2022-09-13

申请号：US16723142

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Vuk Lesi ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Manoj Sastry ,  Liuyang Yang ,  Xiruo Liu

IPC: G06F11/00 ,  H04L9/40 ,  G05B19/042 ,  G05D1/00

Abstract: Systems, methods, computer-readable storage media, and apparatuses to provide active attack detection in autonomous vehicle networks. An apparatus may comprise a plurality of electronic control units communicably coupled by a network, and logic, at least a portion of which is implemented in hardware, the logic to: receive an indication from a first electronic control unit (ECU) of the plurality of ECUs specifying to transmit a first data frame via the network, determine, based on a message identifier (ID) of the first ECU, whether a transmit window for the first ECU is open, and permit the first ECU to transmit the first data frame via the network based on a determination that the transmit window for the first ECU is open.

公开(公告)号：US20220277077A1

公开(公告)日：2022-09-01

申请号：US17742865

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Marcio Juliato ,  Manoj Sastry ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Qian Wang ,  Vuk Lesi

IPC: G06F21/55 ,  G06F21/85 ,  G06F21/71

Abstract: A platform comprising numerous reconfigurable circuit components arranged to operate as primary and redundant circuits is provided. The platform further comprises security circuitry arranged to monitor the primary circuit for anomalies and reconfigurable circuit arranged to disconnect the primary circuit from a bus responsive to detection of an anomaly. Furthermore, the present disclosure provides for the quarantine, refurbishment and designation as redundant, the anomalous circuit.