公开(公告)号：US20220293143A1

公开(公告)日：2022-09-15

申请号：US17805264

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

公开(公告)号：US20220230698A1

公开(公告)日：2022-07-21

申请号：US17647152

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12

Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US20220172756A1

公开(公告)日：2022-06-02

申请号：US17548163

申请日：2021-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20220066874A1

公开(公告)日：2022-03-03

申请号：US17412050

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G11C11/409

Abstract: Described apparatuses and methods provide error correction code (ECC) circuitry that is shared between two or more memory banks of a memory, such as a low-power dynamic random-access memory (DRAM). A memory device may include one or more dies, and a die can have multiple memory banks. The ECC circuitry can service at least two memory banks by producing ECC values based on respective data stored in the two memory banks. By sharing the ECC circuitry, instead of including a per-bank ECC engine, a total die area allocated to ECC functionality can be reduced. Thus, the ECC circuitry can be elevated from a one-bit ECC algorithm to a multibit ECC algorithm, which may increase data reliability. In some cases, memory architecture may operate in environments in which a masked-write command or an internal read-modify-write operation is precluded, including with shared ECC circuitry.

公开(公告)号：US20220066700A1

公开(公告)日：2022-03-03

申请号：US17458068

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

公开(公告)号：US20210407572A1

公开(公告)日：2021-12-30

申请号：US17338458

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira S. Malik ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G11C11/4074 ,  H02M3/156 ,  H01L27/108 ,  H01L25/065

Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

公开(公告)号：US20210151088A1

公开(公告)日：2021-05-20

申请号：US17155434

申请日：2021-01-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US10957367B2

公开(公告)日：2021-03-23

申请号：US16167303

申请日：2018-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20210027819A1

公开(公告)日：2021-01-28

申请号：US17071107

申请日：2020-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US10825495B2

公开(公告)日：2020-11-03

申请号：US16735543

申请日：2020-01-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.