公开(公告)号：US20250130877A1

公开(公告)日：2025-04-24

申请号：US18790795

申请日：2024-07-31

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim ,  Donald Morgan ,  Victor Wong

IPC: G06F11/07

Abstract: Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations. This is beneficial by conserving resources for refreshing victim rows that are identified based on valid usage-based-disturbance data.

公开(公告)号：US20250118358A1

公开(公告)日：2025-04-10

申请号：US18746339

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Toby D. Robbs ,  Christopher J. Kawamura ,  Kang-Yong Kim

IPC: G11C11/4097 ,  G11C7/06 ,  G11C7/18

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

公开(公告)号：US20250004875A1

公开(公告)日：2025-01-02

申请号：US18829593

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Keun Soo Song ,  Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: Described apparatuses and methods provide configurable error correction code (ECC) circuitry and schemes that can utilize a shared ECC engine between multiple memory banks of a memory, including a low-power double data rate (LPDDR) memory. A memory device may include one or more dies with multiple memory banks. The configurable ECC circuitry can use an ECC engine that services a memory bank by producing ECC values based on data stored in the memory bank when data-masking functionality is enabled. When data-masking functionality is disabled, the configurable ECC circuitry can use the shared ECC engine that services at least two memory banks by producing ECC values with a larger quantity of bits based on respective data stored in the at least two memory banks. By using the shared ECC engine responsive to the data-masking functionality being disabled, the ECC functionality can provide higher data reliability with lower die area utilization.

公开(公告)号：US12164795B2

公开(公告)日：2024-12-10

申请号：US18390844

申请日：2023-12-20

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Kang-Yong Kim

IPC: G06F12/00 ,  G06F3/06

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

公开(公告)号：US12131768B2

公开(公告)日：2024-10-29

申请号：US17896337

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Yang Lu

IPC: G11C11/406 ,  G11C11/4078 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4078 ,  G11C11/4085

Abstract: Systems and methods for multi-wordline direct refresh operations in response to a row hammer error in a memory bank. The approach includes detecting, by a row hammer mitigation component, a row hammer error in a memory bank; and then triggering, by the row hammer mitigation component, a response to the row hammer error. Further, a memory controller receives, from a mode register, data, based on an aliasing row counter policy, selecting a type of multi-wordline direct refresh operation to be performed on a plurality of victim memory rows within the memory bank, wherein the plurality of victim memory rows are dispersed across a plurality of memory sub-banks. The approach includes concurrently executing the selected multi-wordline direct refresh operation to the plurality of victim memory rows.

公开(公告)号：US12125517B2

公开(公告)日：2024-10-22

申请号：US17804414

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US20240339152A1

公开(公告)日：2024-10-10

申请号：US18627960

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim ,  Wonjun Choi

IPC: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

公开(公告)号：US20240321329A1

公开(公告)日：2024-09-26

申请号：US18680550

申请日：2024-05-31

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G11C7/10 ,  G11C29/46

CPC classification number: G11C7/1063 ,  G11C7/1066 ,  G11C7/1096 ,  G11C29/46

Abstract: Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：US20240192862A1

公开(公告)日：2024-06-13

申请号：US18582356

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

公开(公告)号：US20240177745A1

公开(公告)日：2024-05-30

申请号：US18520189

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Yuan He ,  Kang-Yong Kim

IPC: G11C7/08 ,  G11C7/10 ,  G11C29/52

CPC classification number: G11C7/08 ,  G11C7/1069 ,  G11C29/52

Abstract: Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.