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105 条记录 (耗时 0.03 秒)

    Modulation coding and decoding
    101.
    发明授权
    Modulation coding and decoding 有权
    调制编码和解码

    公开(公告)号：US07786905B2

    公开(公告)日：2010-08-31

    申请号：US12262345

    申请日：2008-10-31

    申请人： Thomas Mittelholzer

    发明人： Thomas Mittelholzer

    IPC分类号： H03M5/00

    CPC分类号： H03M5/145 ,  H03M5/20

    摘要： Methods and apparatus are provided for partitioning a stream of binary input data into two binary output streams for supply to respective modulation encoders in a modulation coding system. A 4-ary enumerative encoding algorithm is applied to each of a succession of input words in the input bit-stream to produce a succession of 4-ary output symbols from the input word. The 4-ary algorithm simultaneously encodes respective j=∞ Fibonacci codes in the odd and even interleaves of the input word such that the two bit-sequences formed by respective corresponding bits of the succession of output symbols are range-limited codewords. The two binary output streams are then produced by separating the two range-limited codewords generated from each successive input word. The binary output streams can then be independently encoded by respective modulation encoders, and the encoder outputs interleaved to produce a modulation-constrained output stream. Corresponding decoding systems are also provided.

    摘要翻译： 提供了用于将二进制输入数据流划分成两个二进制输出流以提供给调制编码系统中的相应调制编码器的方法和装置。 4进制枚举编码算法被应用于输入比特流中的一系列输入字中的每一个，以从输入字产生一连串的4元输出符号。 4进制算法同时对输入字的奇数和偶数交错中的各个j =∞斐波那契编码进行编码，使得由输出符号序列的相应对应位形成的两个比特序列是范围限制码字。 然后通过分离从每个连续输入字产生的两个范围限制码字来产生两个二进制输出流。 二进制输出流然后可以由相应的调制编码器独立地编码，并且编码器输出被交织以产生调制约束的输出流。 还提供了相应的解码系统。

    Data storage systems
    102.
    发明授权
    Data storage systems 失效
    数据存储系统

    公开(公告)号：US07574646B2

    公开(公告)日：2009-08-11

    申请号：US11286582

    申请日：2005-11-25

    申请人： Roy D. Cideciyan ,  Ajay Dholakia ,  Evangelos S. Eleftheriou ,  Thomas Mittelholzer

    发明人： Roy D. Cideciyan ,  Ajay Dholakia ,  Evangelos S. Eleftheriou ,  Thomas Mittelholzer

    IPC分类号： H03M13/00

    CPC分类号： G11B20/1833

    摘要： A method for decoding data in a data storage system includes generating an output bit stream; generating a first error corrected bit stream in dependence on the output bit stream; generating a second error corrected bit stream in dependence on the first error corrected bit stream; generating a checksum in dependence of the second error corrected bit stream; and, in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave: supplying data indicative of locations of correct bits in the second error corrected bit stream; and, regenerating the first error corrected bit stream in dependence on the pinning data.

    摘要翻译： 一种用于在数据存储系统中解码数据的方法包括：生成输出比特流; 根据输出比特流产生第一纠错比特流; 根据第一纠错比特流产生第二纠错比特流; 根据第二纠错比特流产生校验和; 并且在所述校验和指示所述第二纠错比特流中的错误并且所述第二纠错比特流包括至少一个正确交错的情况下：提供指示所述第二纠错比特流中的正确比特的位置的数据; 以及根据钉扎数据再生第一纠错比特流。

    Data coding for data storage systems
    105.
    发明授权
    Data coding for data storage systems 失效
    数据存储系统的数据编码

    公开(公告)号：US06812867B2

    公开(公告)日：2004-11-02

    申请号：US10455696

    申请日：2003-06-05

    申请人： Roy D Cideciyan ,  Ajay Dholakia ,  Evangelos S Eleftheriou ,  Richard L Galbraith ,  Thomas Mittelholzer ,  Travis R Oenning ,  David J Stanek

    发明人： Roy D Cideciyan ,  Ajay Dholakia ,  Evangelos S Eleftheriou ,  Richard L Galbraith ,  Thomas Mittelholzer ,  Travis R Oenning ,  David J Stanek

    IPC分类号： H03M700

    CPC分类号： H03M7/46 ,  G11B20/1426 ,  G11B2020/1446 ,  H03M5/145

    摘要： Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.

    摘要翻译： 描述了一种具有有限状态机的调制编码器，用于将输入比特转换成输出比特，其中交替输出比特的数量被限制为j + 1，其中j是输出比特中的预定义的最大转移数， 类似的输出位被限制为k + 1，其中k是输出位中的非转换的预定最大数量。 调制编码器可以用于将输入比特流转换成输出比特流的编码装置。 这种装置可以包括用于将输入比特流分成第一组比特和第二组比特的分区逻辑。 多个上述调制编码器可以连接到用于将第一组位转换为编码输出位的分割逻辑。 组合逻辑可以连接到或每个调制编码器和用于组合编码的输出位和第二组位的分区逻辑以产生输出比特流。 还描述了对位调制解码器和解码装置。