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公开(公告)号：US12034456B2
公开(公告)日：2024-07-09
申请号：US17952533
申请日：2022-09-26
申请人： Ciena Corporation
CPC分类号： H03M13/1111 , H03M13/098 , H03M13/136 , H03M13/1515 , H03M13/152 , H03M13/6516
摘要： A transmitter generates an encoded vector by encoding a data vector, the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits a signal representing the encoded vector over a communication channel. A receiver determines a vector estimate from the signal and recovers the data vector from the vector estimate by sequentially decoding the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.
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公开(公告)号：US12009837B2
公开(公告)日：2024-06-11
申请号：US18330669
申请日：2023-06-07
申请人： Kioxia Corporation
发明人： Hironori Uchikawa
CPC分类号： H03M13/159 , H03M13/098 , H03M13/1177 , H03M13/1575 , H03M13/2732 , H03M13/2735
摘要： A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.
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公开(公告)号：US11996157B2
公开(公告)日：2024-05-28
申请号：US17375622
申请日：2021-07-14
申请人： SK hynix Inc.
发明人： Choung Ki Song
CPC分类号： G11C29/42 , G06F7/5443 , G06F17/16 , G06N3/063 , H03M13/098 , H03M13/1575 , H03M13/19
摘要： A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate first write data, first write parity, second write data, and second write parity from first write input data and second write input data when a write operation in an operation mode is performed, and generate first converted data and second converted data from first read data, first read parity, second read data, and second read parity when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the first converted data and the second converted data to generate MAC operation result data.
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公开(公告)号：US20240154624A1
公开(公告)日：2024-05-09
申请号：US18413007
申请日：2024-01-15
申请人： Silicon Motion, Inc.
发明人： Tsung-Chieh Yang , Hong-Jung Hsu
CPC分类号： H03M13/098 , G06F11/1072 , G06F11/108 , G11C11/5628 , G11C16/10 , H03M13/1515 , H03M13/611 , G11C16/26
摘要： A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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公开(公告)号：US11916570B1
公开(公告)日：2024-02-27
申请号：US17985361
申请日：2022-11-11
CPC分类号： H03M13/098 , H03M13/611
摘要： The present disclosure generally relates to a codeword format for data storage and to methods and circuits for generating a codeword based on data to be written in memory and extracting data from a codeword read from memory. In an example, an integrated circuit includes a memory system and a controller circuit. The controller circuit is communicatively coupled to the memory system and is configured to: receive multi-bit data; generate a codeword based on the multi-bit data; and transmit to the memory system the codeword for writing to memory. The codeword has a format that includes first bit positions for the multi-bit data, second bit positions for a bitwise inversion of the multi-bit data, a third bit position for an odd parity value, and a fourth bit position for an even parity value. The odd and even parity values indicate an odd and even parity, respectively, of the multi-bit data.
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公开(公告)号：US11755407B2
公开(公告)日：2023-09-12
申请号：US17331346
申请日：2021-05-26
发明人： Dudy David Avraham , Ran Zamir , Eran Sharon
CPC分类号： G06F11/1068 , H03M13/098 , H03M13/1105 , H03M13/118
摘要： A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.
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公开(公告)号：US11695431B2
公开(公告)日：2023-07-04
申请号：US16661462
申请日：2019-10-23
CPC分类号： H03M13/258 , H03M13/098 , H03M13/2963 , H03M13/617
摘要： A method and a decoder for receiving a message encoded in Turbo Codes and modulated for transmission as an analog signal includes: (a) demodulating the analog signal to recover the Turbo Codes; and (b) decoding the Turbo Codes to recover the message using an iterative Turbo Code decoder, wherein the decoding includes performing an error detection after a predetermined number of iterations of the Turbo Code decoder to determine whether or not an error has occurred during the transmission. The predetermined number of iterations may be, for example, two. Depending on the result of the error detection, the decoding may stop, a request for retransmission of the message may be sent, or further iterations of decoding in the Turbo Code decoder may be carried out.
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公开(公告)号：US11677420B1
公开(公告)日：2023-06-13
申请号：US17683958
申请日：2022-03-01
CPC分类号： H03M13/1125 , H03M13/098 , H03M13/1114 , H03M13/1128
摘要： Example systems, read channel circuits, data storage devices, and methods to use inter-symbol interference message passing (ISI-MP) data in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, configured to determine both the first most likely and second most likely sets of symbols and output inter-symbol interference data based on the adjacent symbols and corresponding ISI in each set of symbols. The inter-symbol interference data may be used by an ISI-MP circuit configured to model ISI-MP and provide feedback to an iterative decoder during local iterations.
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公开(公告)号：US11677419B2
公开(公告)日：2023-06-13
申请号：US17623441
申请日：2020-06-30
申请人： Accelercomm Limited
发明人： Robert Maunder , Matthew Brejza
CPC分类号： H03M13/091 , H03M13/617 , H03M13/098 , H03M13/1168 , H03M13/1575
摘要： A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.
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公开(公告)号：US20190026182A1
公开(公告)日：2019-01-24
申请号：US16141708
申请日：2018-09-25
发明人： Chandra C. Varanasi
CPC分类号： G06F11/1072 , G06F11/1012 , G11C16/06 , G11C29/42 , G11C29/52 , G11C2029/0411 , H03M13/098 , H03M13/152 , H03M13/154 , H03M13/2906 , H03M13/2909
摘要： Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.
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