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    Dense optical flow processing in a computer vision system
    101.
    发明授权
    Dense optical flow processing in a computer vision system 有权

    公开(公告)号：US11620757B2

    公开(公告)日：2023-04-04

    申请号：US17533256

    申请日：2021-11-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Anish Reghunath ,  Michael Peter Lachmayr

    IPC: G06T7/20 ,  G06T7/246 ,  G06T7/269

    Abstract: A computer vision system is provided that includes an image generation device configured to generate consecutive two dimensional (2D) images of a scene, and a dense optical flow engine (DOFE) configured to determine a dense optical flow map for pairs of the consecutive 2D images, wherein, for a pair of consecutive 2D images, the DOFE is configured to perform a predictor based correspondence search for each paxel in a current image of the pair of consecutive 2D images, wherein, for an anchor pixel in each paxel, the predictor based correspondence search evaluates a plurality of predictors to select a best matching pixel in a reference image of the pair of consecutive 2D images, and determine optical flow vectors for each pixel in a paxel based on the best matching pixel selected for the anchor pixel of the paxel.

    Method and apparatus of HEVC de-blocking filter
    102.
    发明授权
    Method and apparatus of HEVC de-blocking filter 有权

    公开(公告)号：US11611764B2

    公开(公告)日：2023-03-21

    申请号：US17330840

    申请日：2021-05-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

    IPC: H04N19/176 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/117 ,  H04N19/186

    Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

    Local memory use for perspective transform engine
    103.
    发明授权
    Local memory use for perspective transform engine 有权

    公开(公告)号：US11537299B2

    公开(公告)日：2022-12-27

    申请号：US17233361

    申请日：2021-04-16

    Applicant: Texas Instruments Incorporated

    Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Rajasekhar Reddy Allu

    IPC: G06F3/06 ,  G06F13/28

    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.

    Image processing accelerator
    105.
    发明授权
    Image processing accelerator 有权

    公开(公告)号：US11237991B2

    公开(公告)日：2022-02-01

    申请号：US16995364

    申请日：2020-08-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

    IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

    METHODS AND APPARATUS TO EXTEND LOCAL BUFFER OF A HARDWARE ACCELERATOR
    106.
    发明申请
    METHODS AND APPARATUS TO EXTEND LOCAL BUFFER OF A HARDWARE ACCELERATOR 有权

    公开(公告)号：US20210326276A1

    公开(公告)日：2021-10-21

    申请号：US17138740

    申请日：2020-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

    IPC: G06F13/16 ,  G06F13/28

    Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

    METHODS AND APPARATUS FOR IMAGE FRAME FREEZE DETECTION
    109.
    发明申请
    METHODS AND APPARATUS FOR IMAGE FRAME FREEZE DETECTION 有权

    公开(公告)号：US20210136358A1

    公开(公告)日：2021-05-06

    申请号：US16669138

    申请日：2019-10-30

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Brian Chae ,  Mihir Mody ,  Rajasekhar Reddy Allu

    IPC: H04N17/00 ,  H04N5/14 ,  H04N7/18

    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.

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