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    Debug for multi-threaded processing
    1.
    发明授权
    Debug for multi-threaded processing 有权

    公开(公告)号：US11144417B2

    公开(公告)日：2021-10-12

    申请号：US16236745

    申请日：2018-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

    IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F9/48 ,  G06F13/28 ,  G06F13/16

    Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

    DEBUG FOR MULTI-THREADED PROCESSING
    2.
    发明申请
    DEBUG FOR MULTI-THREADED PROCESSING 审中-公开

    公开(公告)号：US20200210301A1

    公开(公告)日：2020-07-02

    申请号：US16236745

    申请日：2018-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： NIRAJ NANDAN ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

    IPC: G06F11/273 ,  G06F11/22 ,  G06F13/16 ,  G06F13/28 ,  G06F9/48

    Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

    Image processing accelerator
    3.
    发明授权
    Image processing accelerator 有权

    公开(公告)号：US11237991B2

    公开(公告)日：2022-02-01

    申请号：US16995364

    申请日：2020-08-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

    IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

    Integer and half clock step division digital variable clock divider
    4.
    发明授权
    Integer and half clock step division digital variable clock divider 有权
    整数和半时钟分频数字可变时钟分频器

    公开(公告)号：US08598932B2

    公开(公告)日：2013-12-03

    申请号：US13888050

    申请日：2013-05-06

    Applicant: Texas Instruments Incorporated

    Inventor： Ramakrishnan Venkatasubramanian ,  Anthony Lell ,  Raguram Damodaran

    IPC: G06F1/04 ,  H03K21/00

    CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

    Abstract: A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

    Abstract translation: 提供了一个时钟分频器，其配置为将高速输入时钟信号除以奇数，偶数或分数分频比。 例如，输入时钟可以具有1GHz或更高的时钟周期频率。 输入时钟信号被分割以产生输出时钟信号，首先接收表示分频比N的除法因子值F，其中N可以是奇数或偶数整数。 分数指示符表示分数指示符为1时的分频比为N.5，当分数指示符为零时表示分频比为N。 对于分数除数，F被设置为2（N.5）/ 2，并且对于整数分频比，F被设置为N / 2。 当N为偶数时，每N / 2个输入时钟周期，计数指示器被置位。 当N为奇数时，计数指示灯交替显示N / 2个输入时钟周期，然后1 + N / 2个输入时钟周期。 当分数指示符表示分频比为N.5时，响应于计数指示符的每个断言，合成输出时钟信号的一个周期。 当分数指示符表示分频比是整数时，响应于计数指示符的两个断言，合成输出时钟信号的一个周期。

    Debug for multi-threaded processing
    5.
    发明授权
    Debug for multi-threaded processing 有权

    公开(公告)号：US12204425B2

    公开(公告)日：2025-01-21

    申请号：US18243421

    申请日：2023-09-07

    Applicant: Texas Instruments Incorporated

    Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Mody ,  Gary Cooper ,  Anthony Lell

    IPC: G06F11/00 ,  G06F9/48 ,  G06F11/22 ,  G06F11/273 ,  G06F13/16 ,  G06F13/28

    Abstract: A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.

    Integrated circuit with debugger and arbitration interface
    6.
    发明授权
    Integrated circuit with debugger and arbitration interface 有权

    公开(公告)号：US12204393B2

    公开(公告)日：2025-01-21

    申请号：US18505037

    申请日：2023-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Jose Luis Flores ,  Gary Augustine Cooper ,  Amritpal Singh Mundra ,  Anthony Lell ,  Jason Lynn Peck

    IPC: G06F11/00 ,  G06F1/3203 ,  G06F11/36

    Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

    Image processing accelerator
    7.
    发明授权
    Image processing accelerator 有权

    公开(公告)号：US10747692B2

    公开(公告)日：2020-08-18

    申请号：US16234508

    申请日：2018-12-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

    IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

    Image processing accelerator
    9.
    发明授权
    Image processing accelerator 有权

    公开(公告)号：US12111778B2

    公开(公告)日：2024-10-08

    申请号：US17558252

    申请日：2021-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

    IPC: G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  H04N5/765

    CPC classification number: G06F13/1668 ,  G06F13/28 ,  G06T1/20 ,  H04N5/765

    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

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