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公开(公告)号：US10949357B2
公开(公告)日：2021-03-16
申请号：US16256821
申请日：2019-01-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Gregory Raymond Shurtz , Mihir Narendra Mody , Charles Lance Fuoco , Donald E. Steiss , Jonathan Elliot Bergsagel , Jason A. T. Jones
IPC: G06F12/1027 , G06F9/455 , G06F12/1036
Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.
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公开(公告)号：US10747692B2
公开(公告)日：2020-08-18
申请号：US16234508
申请日：2018-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Mody , Niraj Nandan , Hetul Sanghvi , Brian Chae , Rajasekhar Reddy Allu , Jason A. T. Jones , Anthony Lell , Anish Reghunath
Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.
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公开(公告)号：US11853772B2
公开(公告)日：2023-12-26
申请号：US17888533
申请日：2022-08-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Denis Roland Beaudoin , Gregory Raymond Shurtz , Santhanakrishnan Badri Narayanan , Mark Adrian Bryans , Mihir Narendra Mody , Jason A. T. Jones , Jayant Thakur
IPC: G06F9/4401 , H04L45/00 , H04L47/32 , G06F13/28 , H04L49/351
CPC classification number: G06F9/4418 , G06F9/4406 , G06F13/28 , H04L45/54 , H04L45/66 , H04L47/32 , H04L49/351
Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.
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公开(公告)号：US11715188B1
公开(公告)日：2023-08-01
申请号：US17682735
申请日：2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Veeramanikandan Raju , Niraj Nandan , Samuel Paul Visalli , Jason A. T. Jones , Kedar Satish Chitnis , Gregory Raymond Shurtz , Prithvi Shankar Yeyyadi Anantha , Sriramakrishnan Govindarajan
CPC classification number: G06T7/0002 , G05B23/0259 , G06T1/20 , G06T3/40 , G06T7/97 , G06T2207/10016 , H04N17/00
Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.
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公开(公告)号：US11609866B2
公开(公告)日：2023-03-21
申请号：US17073925
申请日：2020-10-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Kishon Vijay Abraham Israel Vijayponraj , Mihir Narendra Mody , Jason A. T. Jones
Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.
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Patent Agency Ranking
公开(公告)号：US11960416B2
公开(公告)日：2024-04-16
申请号：US17558278
申请日：2021-12-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Daniel Brad Wu , Abhishek Shankar , Mihir Narendra Mody , Gregory Raymond Shurtz , Jason A. T. Jones , Hemant Vijay Kumar Hariyani
IPC: G06F13/16
CPC classification number: G06F13/1647
Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.
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公开(公告)号：US11551399B2
公开(公告)日：2023-01-10
申请号：US17015172
申请日：2020-09-09
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Ajay Jayaraj , Hemant Hariyani , Anand Balagopalakrishnan , Jason A. T. Jones , Erick Zadiel Narvaez
Abstract: Methods, apparatus, systems and articles of manufacture to perform graphics processing on combinations of graphic processing units and digital signal processors are disclosed. A disclosed example method includes processing first data representing input vertices to create second data, the first data using a first format organized by vertex, the second data using a second format organized by components of the vertices. A digital signal processor (DSP) is to perform vertex shading on the second data to create third data, the third data formatted using the second format, the vertex shading performed by executing a first instruction at the DSP, the first instruction generated based on a second instruction capable of being executed at a graphics processing unit (GPU). The third data is processed to create fourth data, the fourth data formatted using the first format.
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公开(公告)号：US11163861B2
公开(公告)日：2021-11-02
申请号：US16188560
申请日：2018-11-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Deepak Kumar Poddar , Mihir Mody , Veeramanikandan Raju , Jason A. T. Jones
Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.
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公开(公告)号：US12050541B2
公开(公告)日：2024-07-30
申请号：US18186524
申请日：2023-03-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Kishon Vijay Abraham Israel Vijayponraj , Mihir Narendra Mody , Jason A. T. Jones
CPC classification number: G06F13/1668 , G06F12/10 , G06F13/4022 , G06F13/4221 , G06F13/4282 , G06F2213/0026
Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.
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公开(公告)号：US11436024B2
公开(公告)日：2022-09-06
申请号：US16700254
申请日：2019-12-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriramakrishnan Govindarajan , Denis Roland Beaudoin , Gregory Raymond Shurtz , Santhanakrishnan Badri Narayanan , Mark Adrian Bryans , Mihir Narendra Mody , Jason A. T. Jones , Jayant Thakur
IPC: G06F9/4401 , H04L45/00 , H04L47/32 , G06F13/28 , H04L49/351
Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.
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