公开(公告)号：US20190393357A1

公开(公告)日：2019-12-26

申请号：US16235987

申请日：2018-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US10403550B2

公开(公告)日：2019-09-03

申请号：US15885359

申请日：2018-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US10374059B2

公开(公告)日：2019-08-06

申请号：US15692124

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  Shao-Ming Yu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.

公开(公告)号：US10355102B2

公开(公告)日：2019-07-16

申请号：US15941798

申请日：2018-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  Wei-Sheng Yun ,  Chen-Feng Hsu ,  Tzu-Chiang Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.