公开(公告)号：US11348920B2

公开(公告)日：2022-05-31

申请号：US17066424

申请日：2020-10-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Li Chiang ,  Szu-Wei Huang ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device includes a first source/drain structure, a channel layer, a second source/drain structure, a gate structure and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on opposite first and second sidewalls of the channel layer when viewed in a first cross-section taken along a first direction. The gate structure is also on a third sidewall of the channel layer but absent from a fourth sidewall of the channel layer when viewed in a second cross-section taken along a second direction different from the first direction. The epitaxial layer is on the fourth sidewall of the channel layer when viewed in the second cross-section and forming a P-N junction with the channel layer.

公开(公告)号：US11043423B2

公开(公告)日：2021-06-22

申请号：US16595007

申请日：2019-10-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC分类号： H01L21/8234 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

摘要： A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US11183599B2

公开(公告)日：2021-11-23

申请号：US16657693

申请日：2019-10-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： I-Sheng Chen ,  Szu-Wei Huang ,  Hung-Li Chiang ,  Cheng-Hsien Wu ,  Chih Chieh Yeh

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/04

摘要： A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.

公开(公告)号：US20200035562A1

公开(公告)日：2020-01-30

申请号：US16595007

申请日：2019-10-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC分类号： H01L21/8234 ,  H01L29/786 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

摘要： A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US10269800B2

公开(公告)日：2019-04-23

申请号：US15605983

申请日：2017-05-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Li Chiang ,  Szu-Wei Huang ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234

摘要： A semiconductor device includes a substrate, a well on the substrate and an FFT on the well. The FET includes a first source/drain, a vertical channel layer, a gate structure, a second source/drain and a body structure. The first source/drain is on the well. The vertical channel layer extends form the first source/drain. The first gate structure surrounds a first portion of sidewalls of the vertical channel layer. The second source/drain is on the vertical channel layer. The body structure is in physical contact with the vertical channel layer. The body structure and the vertical channel layer constitute a bipolar device.

公开(公告)号：US11195763B2

公开(公告)日：2021-12-07

申请号：US16556096

申请日：2019-08-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US11158542B2

公开(公告)日：2021-10-26

申请号：US16676871

申请日：2019-11-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Tung-Ying Lee ,  Szu-Wei Huang ,  Huan-Sheng Wei

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/04

摘要： Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.

公开(公告)号：US10804268B2

公开(公告)日：2020-10-13

申请号：US16391152

申请日：2019-04-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Li Chiang ,  Szu-Wei Huang ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

摘要： A semiconductor device includes a substrate, a first source/drain structure, a vertical channel layer, a gate structure, a second source/drain structure and a body epitaxial layer. The first source/drain structure is over the substrate. The vertical channel layer is over the first source/drain structure. The gate structure is on a first sidewall of the vertical channel layer. The second source/drain structure is over the vertical channel layer. The body epitaxial layer is on a second sidewall of the vertical channel layer. The body epitaxial layer and the vertical channel layer are of opposite conductivity types, and the body epitaxial layer is separated from the gate structure.

公开(公告)号：US10438851B2

公开(公告)日：2019-10-08

申请号：US16048581

申请日：2018-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L29/49

摘要： A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US10403550B2

公开(公告)日：2019-09-03

申请号：US15885359

申请日：2018-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC分类号： H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

摘要： In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.