公开(公告)号：US20130212438A1

公开(公告)日：2013-08-15

申请号：US13369563

申请日：2012-02-09

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F11/36

CPC分类号： G06F11/3636 ,  G06F11/3648

摘要： During a debug mode of operation of a data processor it is determined whether a data access request is to a stack of the data processor. If not, a data trace message based on the data access request is generated for transmission to a debugger so long as an address being accessed by data access request meets a predefined address range criteria. Otherwise, if the data access request is to the stack of the data processor, a data trace message based on the data access request is prevented from being generated for transmission to the debugger regardless the predefined address range criteria.

摘要翻译： 在数据处理器的调试操作模式期间，确定数据访问请求是否是数据处理器的堆栈。 如果不是，则只要由数据访问请求访问的地址满足预定义的地址范围标准，则生成基于数据访问请求的数据跟踪消息用于传输到调试器。 否则，如果数据访问请求是数据处理器的堆栈，则防止基于数据访问请求的数据跟踪消息被生成用于发送到调试器，而不管预定义的地址范围标准。

公开(公告)号：US08423721B2

公开(公告)日：2013-04-16

申请号：US12112508

申请日：2008-04-30

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F12/08

CPC分类号： G06F13/28 ,  G06F12/0804 ,  G06F12/0833

摘要： A method includes detecting a bus transaction on a system interconnect of a data processing system having at least two masters; determining whether the bus transaction is one of a first type of bus transaction or a second type of bus transaction, where the determining is based upon a burst attribute of the bus transaction; performing a cache coherency operation for the bus transaction in response to the determining that the bus transaction is of the first type, where the performing the cache coherency operation includes searching at least one cache of the data processing system to determine whether the at least one cache contains data associated with a memory address the bus transaction; and not performing cache coherency operations for the bus transaction in response to the determining that the bus transaction is of the second type.

摘要翻译： 一种方法包括检测具有至少两个主器件的数据处理系统的系统互连上的总线事务; 确定总线事务是否是第一类型的总线事务或第二类型的总线事务之一，其中确定基于总线事务的突发属性; 响应于确定总线事务是第一类型，执行总线事务的高速缓存一致性操作，其中执行高速缓存一致性操作包括搜索数据处理系统的至少一个高速缓存以确定该至少一个高速缓存 包含与内存地址相关的数据总线事务; 并且响应于确定总线事务是第二类型而不对总线事务执行高速缓存一致性操作。

公开(公告)号：US08407457B2

公开(公告)日：2013-03-26

申请号：US11864292

申请日：2007-09-28

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F9/00

CPC分类号： G06F11/36 ,  G06F9/3861

摘要： A system has a pipelined processor for executing a plurality of instructions by sequentially fetching, decoding, executing and writing results associated with execution of each instruction. Debug circuitry is coupled to the pipelined processor for monitoring execution of the instructions to determine when a debug event occurs. The debug circuitry generates a debug exception to interrupt instruction processing flow. The debug circuitry has control circuitry for indicating a number of instructions, if any, that complete instruction execution between an instruction that caused the debug event and a point in instruction execution when the exception is taken.

摘要翻译： 系统具有流水线处理器，用于通过顺序地取出，解码，执行和写入与每个指令的执行相关联的结果来执行多个指令。 调试电路耦合到流水线处理器，用于监视指令的执行以确定调试事件何时发生。 调试电路产生调试异常以中断指令处理流程。 调试电路具有用于指示在执行异常时在导致调试事件的指令与指令执行点之间完成指令执行的指令数量（如果有的话）的数量的控制电路。

公开(公告)号：US20130047037A1

公开(公告)日：2013-02-21

申请号：US13210281

申请日：2011-08-15

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F11/36

CPC分类号： G06F11/3656

摘要： Software executed at a data processor unit includes a software debugger. The software debugger can be assigned responsibility for servicing a debug event, and be authorized to allow software control of debug event resources associated with the debug event. An indicator, when asserted, prevents a authorized request by software to control a debug event resource.

摘要翻译： 在数据处理器单元处执行的软件包括软件调试器。 软件调试器可以分配负责维修调试事件，并被授权允许软件控制与调试事件相关联的调试事件资源。 一个指示符，当被断言时，阻止软件授权的请求来控制调试事件资源。

公开(公告)号：US20130007533A1

公开(公告)日：2013-01-03

申请号：US13170289

申请日：2011-06-28

申请人： Gary L. Miller ,  Mark Maiolani ,  William C. Moyer

发明人： Gary L. Miller ,  Mark Maiolani ,  William C. Moyer

IPC分类号： G06F11/34

CPC分类号： G06F11/263 ,  G06F11/3466

摘要： A system includes a processor configured to execute a first interrupt; an interrupt controller, coupled to the processor, and configured to store one or more pending interrupts; and a sequence processing unit, coupled to the processor and the interrupt controller, and configured to receive an identifier of the first interrupt, receive an identifier corresponding to each of the one or more pending interrupts, and provide trigger information to a state condition logic in response to one or more of the identifiers of the one or more pending interrupts and the identifier of the first interrupt, wherein the trigger information is used to determine a trace or debug action responsive to the trigger information.

摘要翻译： 一种系统，包括配置成执行第一中断的处理器; 中断控制器，其耦合到所述处理器，并且被配置为存储一个或多个挂起的中断; 以及序列处理单元，其耦合到所述处理器和所述中断控制器，并且被配置为接收所述第一中断的标识符，接收对应于所述一个或多个挂起中断中的每一个的标识符，并且向所述处理器和所述中断控制器中的状态条件逻辑提供触发信息 响应于一个或多个待决中​​断的标识符和第一中断的标识符，其中触发信息用于响应于触发信息来确定跟踪或调试动作。

公开(公告)号：US20120311380A1

公开(公告)日：2012-12-06

申请号：US13149304

申请日：2011-05-31

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F11/16 ,  G06F12/08

CPC分类号： G06F11/073 ,  G06F11/0772 ,  G06F11/0793 ,  G06F12/0888 ,  G06F2212/1032

摘要： Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators.

摘要翻译： 高速缓存的每个高速缓存线具有锁定状态，该状态指示是否已经检测到在高速缓存行中访问的数据的错误，并且还具有数据有效性状态，其指示存储在高速缓存行中的数据是否表示当前值 的数据存储在相应的存储器位置。 高速缓存行的锁定状态由与高速缓存行相关联的一个或多个锁定位的集合指示。 响应于缓存无效事件，可以维护每个高速缓存行的锁定指示符的状态，使得即使在高速缓存无效之后，锁定的高速缓存行也保持在锁定状态。 这使得在数据处理设备处执行的存储器错误管理软件可以鲁棒地管理锁定指示器的状态。

公开(公告)号：US08327082B2

公开(公告)日：2012-12-04

申请号：US12201225

申请日：2008-08-29

申请人： William C. Moyer ,  Quyen Pho

发明人： William C. Moyer ,  Quyen Pho

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F2212/1016

摘要： A snoop look-up operation is performed in a system having a cache and a first processor. The processor generates requests to the cache for data. A snoop queue is loaded with snoop requests. Fullness of the snoop queue is a measure of how many snoop requests are in the snoop queue. A snoop look-up operation is performed in the cache if the fullness of the snoop queue exceeds the threshold. The snoop look-up operation is based on a snoop request from the snoop queue corresponding to an entry in the snoop queue. If the fullness of the snoop queue does not exceed the threshold, waiting to perform a snoop look-up operation until an idle access request cycle from the processor to the cache occurs and performing the snoop look-up operation in the cache upon the idle access request cycle from the processor.

摘要翻译： 在具有高速缓存和第一处理器的系统中执行窥探查找操作。 处理器生成对高速缓存数据的请求。 侦听队列加载了窥探请求。 侦听队列的完整性是侦听队列中有多少个窥探请求的度量。 如果侦听队列的充满度超过阈值，则在缓存中执行侦听查找操作。 窥探查找操作基于来自与窥探队列中的条目相对应的窥探队列的窥探请求。 如果侦听队列的充满度不超过阈值，则等待执行窥探查找操作，直到发生从处理器到高速缓存的空闲访问请求周期，并且在空闲访问时执行高速缓存中的窥探查找操作 从处理器请求周期。

公开(公告)号：US20120290806A1

公开(公告)日：2012-11-15

申请号：US13103609

申请日：2011-05-09

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F12/14

CPC分类号： G06F9/30043 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3877

摘要： A data processor is disclosed that accesses its local memory by routing requests through a data path that is external the data processor. A reservation/decoration controller implements specialized handling associated with a received request to access local memory. In addition to implementing special handling, a memory controller that is associated with the reservation/decoration controller routes a corresponding access request back to the data processor core to access its local memory.

摘要翻译： 公开了一种数据处理器，其通过在数据处理器外部的数据路径路由请求来访问其本地存储器。 预约/装饰控制器实现与接收到的访问本地存储器的请求相关联的专门处理。 除了实施特殊处理之外，与预约/装饰控制器相关联的存储器控​​制器将相应的访问请求返回到数据处理器核心以访问其本地存储器。

公开(公告)号：US20120272006A1

公开(公告)日：2012-10-25

申请号：US13090056

申请日：2011-04-19

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F12/08

CPC分类号： G06F11/1658 ,  G06F11/1629 ,  G06F12/0848 ,  G06F12/126 ,  G06F2201/845 ,  G06F2212/1016 ,  G06F2212/1032

摘要： To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.

摘要翻译： 为了促进动态锁步支持，可以增强用于根据替换算法或策略来选择用于替换新分配的特定高速缓存行的替换状态和/或逻辑，以提供用于相应锁步和执行模式的通常独立的替换上下文。 在某些情况下，根据先入先出（FIFO），循环，随机，最近最少使用（LRU），伪LRU的新分配的高速缓存行选择可能是常规的替换逻辑 或其他替换算法/策略至少部分地复制以提供分别覆盖缓存的锁步和性能分区的锁步和性能实例。 在某些情况下，替换逻辑的统一实例可能会在性能和锁步操作模式之间（或与其一致）中的适当状态重新初始化。

公开(公告)号：US08266498B2

公开(公告)日：2012-09-11

申请号：US12415672

申请日：2009-03-31

申请人： William C. Moyer

发明人： William C. Moyer

IPC分类号： G06F11/00

CPC分类号： G06F11/1064

摘要： A cache includes a plurality of cache lines, where each cache line includes a detection type field, corresponding cache data field, a detection field, and a corresponding tag field. The detection type field indicates an error detection scheme from a plurality of error detection schemes currently in use for the corresponding cache data field. One example of an error detection scheme is a multiple bit error detection scheme (e.g. an error detection coding (EDC) or an error correction coding (ECC)). Another type is a single bit error detection scheme (e.g. parity error detection). The detection bits field stores parity bits if parity error detection is used. The detection bits field stores checking bits if EDC coding is used.

摘要翻译： 高速缓存包括多条高速缓存线，其中每条高速缓存线包括检测类型字段，对应的高速缓存数据字段，检测字段和对应的标记字段。 检测类型字段指示当前正在使用的对应的高速缓存数据字段的多个错误检测方案的错误检测方案。 错误检测方案的一个示例是多位错误检测方案（例如，错误检测编码（EDC）或纠错编码（ECC））。 另一种类型是单位错误检测方案（例如奇偶校验错误检测）。 如果使用奇偶校验错误检测，则检测位字段存储奇偶校验位。 如果使用EDC编码，则检测比特字段存储检查比特。