公开(公告)号：US5640393A

公开(公告)日：1997-06-17

申请号：US460319

申请日：1995-06-02

Applicant: William Lo ,  Ian Crayford

Inventor： William Lo ,  Ian Crayford

IPC: H04L9/36 ,  H04L12/22 ,  H04L12/44 ,  H04L12/46 ,  H04L29/06 ,  H04L9/00

CPC classification number: H04L63/02 ,  H04L12/22 ,  H04L12/44 ,  H04L12/4625

Abstract: A secure repeater implementing data packet masking includes a programmable and selective, on a per port basis, disrupt response responsive to any of several selectable qualifying conditions. A disrupt controller receives signals indicating various characteristics of fields of a data packet, and other conditions. A register bank includes a plurality of memories, one associated with each port and some of the conditions, assists the disrupt controller to determine the associated port's disrupt response to the data packet. Each memory stores a disrupt control code. When the disrupt control code for a particular port has a value indicating that the associated port is enabled, deassertion of a condition signal associated with that control code results in disruption of a data packet. A cell array permits simple, efficient scaling and formation of integrated semiconductor structures to implement complex disrupt logic equations.

Abstract translation: 实现数据分组掩蔽的安全中继器包括在每个端口的基础上的可编程和选择性，响应于几种可选择的限定条件中的任一种而中断响应。 中断控制器接收指示数据包的字段的各种特性的信号和其他条件。 寄存器组包括多个存储器，一个与每个端口相关联的存储器和一些条件，帮助中断控制器确定相关端口对数据包的中断响应。 每个存储器存储中断控制代码。 当特定端口的中断控制代码具有指示相关端口被使能的值时，与该控制代码相关联的条件信号的取消取消导致数据分组的中断。 单元阵列允许简单，有效的缩放和形成集成半导体结构以实现复杂的中断逻辑方程。

公开(公告)号：US5559801A

公开(公告)日：1996-09-24

申请号：US438982

申请日：1995-05-11

Applicant: William Lo

Inventor： William Lo

IPC: H04L12/24 ,  H04L12/44 ,  H04J3/06

CPC classification number: H04L41/26 ,  H04L12/44

Abstract: A sampling repeater implementing a data packet sampling schedule includes a repeater front-end, a transmitter and a sampler. The transmitter, responsive to disrupt control signals, retransmits a data packet in a disrupted form, or an undisrupted form, to a management unit coupled to a management port. When one of the disrupt control signals are asserted, the data packet is retransmitted undisrupted as a sample packet. The management unit processes the sample packet and extracts any desired statistics. When none of the disrupt control signals are asserted, the disrupted data packet is retransmitted to the management unit. The disrupted data packet fails error checking and is ignored. The sampler periodically, according to the sampling schedule, asserts one of the disrupt control signals, to pass sample packets to the management unit. Thus, the management unit only processes a subset of the input data packets, rather than every data packet.

Abstract translation: 实现数据分组采样计划的采样中继器包括中继器前端，发射机和采样器。 响应于中断控制信号的发射机以破坏的形式或不间断的形式将数据分组重传到耦合到管理端口的管理单元。 当其中一个中断控制信号被断言时，数据包被重传为中断，作为一个采样包。 管理单元处理样本数据包并提取任何所需的统计信息。 当没有断开控制信号被断言时，中断的数据包被重新发送到管理单元。 中断的数据包失败错误检查，并被忽略。 采样器根据采样计划周期性地定出其中一个中断控制信号，以将采样数据包传送到管理单元。 因此，管理单元仅处理输入数据分组的子集，而不是每个数据分组。

公开(公告)号：US5493562A

公开(公告)日：1996-02-20

申请号：US337635

申请日：1994-11-10

Applicant: William Lo

Inventor： William Lo

IPC: H04L12/56 ,  H04L12/26 ,  H04B17/02 ,  H04J3/14

CPC classification number: H04L43/0847

Abstract: A circuit including a data formatter for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory, a memory for storing the desired information for later access by a microprocessor, and a controller for selectively transferring and writing the desired information from the data formatter to the memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure.

Abstract translation: 一种电路，包括用于接收与数据分组相关联的期望信息并将这些比特排列成用于传送到存储器的格式的数据格式器，用于存储所需信息以供稍后由微处理器访问的存储器，以及用于选择性地传送和写入的控制器 从数据格式化器到存储器的所需信息。 该电路通过仅存储具有错误的数据分组的期望信息来提供改进的性能。 也就是说，除数据分组错误信息（诸如错误条件）之外，数据分组本身内部的信息，诸如源地址和数据分组外部的信息，诸如中继器端口号，可以被存储为 微处理器在其休闲时读取的存储器中的错误统计信息。

公开(公告)号：US5388133A

公开(公告)日：1995-02-07

申请号：US20490

申请日：1993-02-22

Applicant: Nader Vijeh ,  William Lo

Inventor： Nader Vijeh ,  William Lo

IPC: H04L12/28 ,  G06F11/34 ,  H04L12/26 ,  G06M3/06

CPC classification number: H04L12/2602 ,  G06F11/348 ,  H04L43/00 ,  G06F2201/88

Abstract: A counter for attribute stored in an Ethernet system is partitioned such that the storage section is separated from the incrementors section. In so doing, counters are implemented in a significantly less space than if the counters were implemented as individual counters. The counter utilizes random access memory as the storage section and a 32 bit incrementor. As the incrementor section along with a pair of latches to implement the counter.

Abstract translation: 存储在以太网系统中的属性的计数器被分区，使得存储部分与增量部分分离。 在这样做时，计数器的实现方式远远小于将计数器作为单独计数器实现的空间。 该计数器利用随机存取存储器作为存储部分和32位增量器。 作为递增器部分以及用于实现计数器的一对闩锁。

公开(公告)号：US5375089A

公开(公告)日：1994-12-20

申请号：US132027

申请日：1993-10-05

Applicant: William Lo

Inventor： William Lo

IPC: G11C11/401 ,  G06F12/00 ,  G11C8/16 ,  G11C11/41 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/16

Abstract: A plural port memory system utilizing a memory having a write port and a separate read port wherein the write port includes a write data line, a write address, and a write enable line and wherein the read port includes a read data line, a read address, and a read enable line. The plural port memory system includes: a plurality of interfaces for reading from and writing to the memory, each interface having a read request line and a write request line; and a controller coupled to each of the read and write request lines, and the read and write enable lines for arbitrating access to the memory by the plurality of interfaces.

Abstract translation: 一种利用具有写入端口和单独读取端口的存储器的多端口存储器系统，其中写入端口包括写入数据线，写入地址和写入使能线，并且其中读取端口包括读取数据线，读取地址 ，以及读使能线。 多个端口存储器系统包括：多个用于从存储器读取和写入存储器的接口，每个接口具有读取请求行和写入请求行; 以及耦合到读取和写入请求行中的每一个的控制器以及用于通过多个接口仲裁对存储器的访问的读取和写入使能线。

公开(公告)号：US08856391B1

公开(公告)日：2014-10-07

申请号：US12616111

申请日：2009-11-10

Applicant: Trinh T. Phung ,  William Lo

Inventor： Trinh T. Phung ,  William Lo

IPC: G06F13/00 ,  G06F13/14 ,  G06F13/36 ,  H04L12/66

CPC classification number: G06F13/1684

Abstract: An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EEPROMs is written to registers in the physical layer device to configure the physical layer device.

Abstract translation: 符合IEEE 802.3标准的物理层设备提供物理层设备的配置信息的高效加载。 配置信息被写入物理层设备中的易失性存储器中，然后上传到至少一个EEPROM。 配置信息在物理层设备启动期间被下载到易失性存储器。 系统控制器也可以直接访问EEPROM，绕过易失性存储器。 通过在系统控制器和EEPROM之间提供桥接器，并在物理层器件的易失性存储器中提供额外的位，系统控制器可以一次读取一个字节的EEPROM。 在复位期间，将EEPROM的内容写入物理层设备中的寄存器，以配置物理层设备。

公开(公告)号：US08665901B1

公开(公告)日：2014-03-04

申请号：US13280098

申请日：2011-10-24

Applicant: William Lo ,  Francis Campana

Inventor： William Lo ,  Francis Campana

IPC: H04J3/22

CPC classification number: H04L41/0806 ,  H04L12/4013

Abstract: The present invention relates to methods and apparatus for performing reverse auto-negotiation, in which one network device establishes a link with another network device at a preferred operating mode (e.g., the lowest speed) common to both devices without linking twice. The physical layer of a local network device (local PHY) may stall the normal auto-negotiation process with the link partner, while receiving the abilities of the link partner. The local PHY may then transmit a signal having only the preferred common operating mode (e.g., the lowest speed) encoded within. The link partner may then conclude that the local PHY is only capable of the preferred common operating mode (e.g., the lowest speed) and a link between the two devices may be established at that common mode.

Abstract translation: 本发明涉及用于执行反向自动协商的方法和装置，其中一个网络设备在两个设备共同的优选操作模式（例如，最低速度）下建立与另一个网络设备的链路，而不链接两次。 本地网络设备（本地PHY）的物理层可以在接收到链路伙伴的能力的同时阻止与链路伙伴的正常自动协商过程。 本地PHY然后可以发送仅具有在其内编码的优选公共操作模式（例如，最低速度）的信号。 然后，链路伙伴可以得出结论，本地PHY仅能够具有优选的公共操作模式（例如，最低速度），并且可以在该共同模式下建立两个设备之间的链路。

公开(公告)号：US08599679B1

公开(公告)日：2013-12-03

申请号：US12945262

申请日：2010-11-12

Applicant: William Lo

Inventor： William Lo

IPC: H04L1/00

CPC classification number: H04L1/24 ,  H04L43/0823

Abstract: An apparatus including a monitoring module, a first timer, and a first circuit. The monitoring module is configured to (i) monitor a link when the link is up and (ii) detect when the link fails. The first timer is configured to expire in a predetermined time after the link fails. The first circuit is configured to generate an indication that the link is down. The first circuit is configured to generate the indication (i) in response to the monitoring module detecting that the link has failed and (ii) before the first timer expires.

Abstract translation: 一种包括监视模块，第一定时器和第一电路的装置。 监控模块被配置为（i）当链路启动时监控链路，（ii）检测链路何时失败。 第一定时器被配置为在链路发生故障之后的预定时间内过期。 第一电路被配置为产生链路关闭的指示。 第一电路被配置为响应于监视模块检测到链路已经失败并且（ii）在第一定时器期满之前产生指示（i）。

公开(公告)号：US08582443B1

公开(公告)日：2013-11-12

申请号：US12917748

申请日：2010-11-02

Applicant: Junqing Sun ,  Danjin Wu ,  Xiong Fang ,  Baohua Chen ,  William Lo

Inventor： Junqing Sun ,  Danjin Wu ,  Xiong Fang ,  Baohua Chen ,  William Lo

IPC: H04L12/26 ,  H04B3/20

CPC classification number: H04B17/00 ,  G01R27/06 ,  G01R31/11 ,  H04B3/487 ,  H04L43/16 ,  H04L43/50

Abstract: Systems, methods, and other embodiments associated with echo cancellation are described. According to one embodiment, an apparatus includes a cable tester that determines whether a fault in a cable exists by using echo cancellation values.

Abstract translation: 描述与回波抵消相关联的系统，方法和其他实施例。 根据一个实施例，一种装置包括电缆测试器，其通过使用回波消除值来确定电缆中的故障是否存在。

公开(公告)号：US08576865B1

公开(公告)日：2013-11-05

申请号：US13174096

申请日：2011-06-30

Applicant: William Lo ,  Sehat Sutardja

Inventor： William Lo ,  Sehat Sutardja

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/66

CPC classification number: H04L49/557 ,  H04L49/30

Abstract: A switch includes a first IC and a second IC. The first IC includes a first set of (N+1) serializer/deserializer (SERDES) modules communicating with a first set of (N+1) SERDES modules of a switch IC; a first set of N SERDES modules communicating with a first set of N ports; and a first set of N multiplexer modules communicating with (i) the first set of N SERDES modules and (ii) the first set of (N+1) SERDES modules of the first IC. The second IC includes a second set of (N+1) SERDES modules communicating with a second set of (N+1) SERDES modules of the switch IC; a second set of N SERDES modules communicating with a second set of N ports; and a second set of N multiplexer modules communicating with (i) the second set of N SERDES modules and (ii) the second set of (N+1) SERDES modules of the second IC.

Abstract translation: 开关包括第一IC和第二IC。 第一IC包括与开关IC的第一组（N + 1）SERDES模块通信的第一组（N + 1）串行器/解串器（SERDES）模块; 与第一组N个端口通信的第一组N SERDES模块; 以及与（i）第一组N个SERDES模块和（ii）第一IC的第（N + 1）个SERDES模块组通信的第一组N个多路复用器模块。 第二IC包括与开关IC的第（N + 1）个SERDES模块通信的第二组（N + 1）SERDES模块; 与第二组N个端口通信的第二组N SERDES模块; 以及第二组N个多路复用器模块，其与（i）第二组N个SERDES模块和（ii）第二IC的第（N + 1）个SERDES模块组通信。