公开(公告)号：US07193461B2

公开(公告)日：2007-03-20

申请号：US10919029

申请日：2004-08-16

申请人： Mohammad Shafiul Mobin ,  Jeffrey H. Saunders ,  Lane A. Smith

发明人： Mohammad Shafiul Mobin ,  Jeffrey H. Saunders ,  Lane A. Smith

IPC分类号： H03F1/26

CPC分类号： H03F1/3241 ,  H03F2200/468

摘要： A pre-distorter that compensates for amplitude and phase distortion created by an amplifier. During a training session, the amplifier is stimulated with input signals of pre-selected amplitude and phase at various temperatures and the amplifier output is captured and converted into data sets. Polynomials are then fitted to the data sets and inverses of the polynomials are determined. The coefficients of the inverse polynomials are then saved for each temperature. During operation, the amplifier temperature is predicted based on the amplifier input signal and the coefficients associated with the predicted temperature are selected to be applied to the input signal to compensate for amplitude and phase distortion caused by the amplifier.

摘要翻译： 一个预失真器，用于补偿放大器产生的幅度和相位失真。 在训练期间，放大器用各种温度的预选幅度和相位的输入信号进行激励，并且放大器输出被捕获并转换为数据集。 然后将多项式拟合到数据集中，并确定多项式的倒数。 然后针对每个温度保存逆多项式的系数。 在操作期间，基于放大器输入信号预测放大器温度，并且选择与预测温度相关联的系数以施加到输入信号以补偿由放大器引起的幅度和相位失真。

公开(公告)号：US06778665B1

公开(公告)日：2004-08-17

申请号：US09414565

申请日：1999-10-08

申请人： Jonathan H. Fischer ,  Donald R. Laturell ,  Lane A. Smith ,  Michael S. Toth ,  Michael G. Williams

发明人： Jonathan H. Fischer ,  Donald R. Laturell ,  Lane A. Smith ,  Michael S. Toth ,  Michael G. Williams

IPC分类号： H04M100

CPC分类号： H04M19/08

摘要： A line powered data access arrangement (DAA) is disclosed which adaptively allows proper operation with power supplied from a telephone line as conditions warrant, while at the same time satisfying the relevant requirements of many countries. In the line powered codec, a startup procedure for the international line powered codec uses register settings, e.g., country-specific register settings, which are powered and maintained from the low voltage side (e.g., from the PC or modem side) of the line powered codec. In this way, even during low line power conditions the programmed state of the line powered codec can be maintained, thus a default condition will not necessarily returned to by the line powered codec upon reset due to a power loss in the telephone line. In another aspect, a charge storage device such as a charge capacitor is charged from a charge pump formed from a differential clock signal from the low voltage side. A current and voltage detection module in the line powered codec is always powered from the telephone line. Upon detection of an off-hook signal or a power down condition, the current detection module determines if/when the current and voltage on the telephone line is sufficient to power certain circuits on the line powered codec. If sufficient power is not present, the line powered codec does not power up. However, the line powered codec will power up if sufficient current is detected. In another aspect, a plurality of power rails may be provided. A first power rail may be associated with the line power, a second power rail may be associated with a low voltage side power source, e.g., a charge storage device. A third (and other) power rails may be switchably connected to either the first power rail or second power rail as line power conditions and on-hook/off-hook conditions warrant.

摘要翻译： 公开了一种线路数据访问安排（DAA），其适应性地允许根据条件允许从电话线路提供的电力进行适当的操作，同时满足许多国家的相关要求。 在线路供电的编解码器中，用于国际线路供电的编解码器的启动过程使用寄存器设置，例如，国家特定寄存器设置，其由线路的低电压侧（例如，从PC或调制解调器侧）供电和维护 电源编解码器。 以这种方式，即使在低功率电力条件下，也可以维护线路供电的编解码器的编程状态，因此由于电话线路中的功率损耗，默认条件不一定由线路供电的编解码器复位。 另一方面，诸如充电电容器的电荷存储装置从由低电压侧的差分时钟信号形成的电荷泵充电。 线路供电编解码器中的电流和电压检测模块始终通过电话线供电。 当检测到摘机信号或断电状态时，电流检测模块确定电话线路上的电流和电压是否足以对线路供电的编解码器上的某些电路供电。 如果没有足够的电源，线路供电的编解码器不会上电。 然而，如果检测到足够的电流，则线路供电的编解码器将上电。 另一方面，可以设置多个电源轨。 第一电力轨可以与线路电力相关联，第二电力轨道可以与低电压侧电源（例如电荷存储装置）相关联。 第三（和其他）电源轨可以切换地连接到第一个电源轨或第二个电源轨，因为线路电源条件和挂机/摘机条件值得。

公开(公告)号：US06728371B1

公开(公告)日：2004-04-27

申请号：US09442544

申请日：1999-11-18

申请人： Jonathan Herman Fischer ,  Keith Eugene Hollenbach ,  Donald Raymond Laturell ,  Lane A. Smith ,  Weilin Zhu

发明人： Jonathan Herman Fischer ,  Keith Eugene Hollenbach ,  Donald Raymond Laturell ,  Lane A. Smith ,  Weilin Zhu

IPC分类号： H04M100

CPC分类号： H04M19/001

摘要： A method and apparatus for a data access arrangement (DAA) which includes a line modulator containing capacitive elements to increase system stability. The invention provides improved stability during system startup and normal system operation. The line modulator is capable of adjusting the AC modulation and the DC termination presented to the telephone line. Capacitive elements are added to the modulator to provide enhanced system stability. The method includes drawing power from the telephone line, modulating the telephone line, sensing a level of distortion through the line modulator, feeding the sensed level of distortion to the line modulator, and using capacitive circuits to provide additional system stability.

摘要翻译： 一种用于数据存取装置（DAA）的方法和装置，其包括一个包含电容元件的线路调制器以增加系统稳定性。 本发明提供了在系统启动和正常系统操作期间的改进的稳定性。 线路调制器能够调整AC调制和提供给电话线的DC终端。 将电容元件添加到调制器以提供增强的系统稳定性。 该方法包括从电话线路中抽取电力，调制电话线路，通过线路调制器感测失真水平，将感测到的失真电平馈送到线路调制器，以及使用电容电路来提供额外的系统稳定性。

公开(公告)号：US06674856B1

公开(公告)日：2004-01-06

申请号：US09401995

申请日：1999-09-23

申请人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

发明人： Paul D. Hendricks ,  Donald R. Laturell ,  Lane A. Smith ,  Steven B. Witmer

IPC分类号： H04M100

CPC分类号： H04M1/68

摘要： The present invention provides a digital pre-distortion filter in arrangement with a data access arrangement (DAA) on the component side (e.g., in a modem chipset). This arrangement of the pre-distortion filter outside of the DAA allows digital processes such as digital emulation of the central office impedance to remain unaffected by the pre-distortion in the transmitted signal, allowing the dynamic range of the transmitted signal to be flattened to minimize return loss without complicating the transfer function of the digital emulation of the central office complex load. In the case of a digital emulation filter, placement of a digital pre-distortion filter outside of an analog-to-digital (A/D) digital-to-analog (D/A) loop also minimizes the noise otherwise associated with the use of a pre-distortion filter. Thus, benefits of a pre-distortion filter can be gained without interfering with emulation of impedance, and without causing a significant amount of noise in the transmitted signal.

摘要翻译： 本发明提供了一种数字预失真滤波器，其配置为在组件侧（例如，调制解调器芯片组）中的数据访问装置（DAA）。 DAA之前的预失真滤波器的这种布置允许诸如中心局阻抗的数字仿真的数字处理不受传输信号中的预失真的影响，允许传输信号的动态范围被平坦化以最小化 返回损耗，而不会使中心局复杂负载的数字仿真传输功能复杂化。 在数字仿真滤波器的情况下，数字预失真滤波器在模数（A / D）数模（D / A）环路之外的放置也使得与使用相关的噪声最小化 的预失真滤波器。 因此，可以获得预失真滤波器的优点而不干扰阻抗的仿真，并且不会在发射信号中引起大量的噪声。

公开(公告)号：US06621904B1

公开(公告)日：2003-09-16

申请号：US09407444

申请日：1999-09-29

申请人： Jonathan Herman Fischer ,  Keith Eugene Hollenbach ,  Donald Raymond Laturell ,  Lane A. Smith ,  Weilin Zhu

发明人： Jonathan Herman Fischer ,  Keith Eugene Hollenbach ,  Donald Raymond Laturell ,  Lane A. Smith ,  Weilin Zhu

IPC分类号： H04M100

CPC分类号： H04M19/005 ,  H04M1/7385

摘要： A circuit provides a modulation signal to an input terminal of a line modulator which places a line current modulated in accordance with the modulation signal on a telephone line. An amplifier of the circuit amplifies an analog input signal to provide the modulation signal at an output terminal. A first resistor and a first capacitor are coupled in series between a first input terminal of the amplifier and the line, and a second resistor and a second capacitor are coupled in series between a second input terminal of the amplifier and the line. First and second precharge amplifiers are used to precharge the first and second capacitors, respectively, to reduce DC setup time.

摘要翻译： 电路向线路调制器的输入端提供调制信号，线路调制器将根据调制信号调制的线路电流放置在电话线路上。 电路的放大器放大模拟输入信号以在输出端提供调制信号。 第一电阻器和第一电容器串联连接在放大器的第一输入端和线路之间，第二电阻器和第二电容器串联耦合在放大器的第二输入端子和线路之间。 第一和第二预充电放大器分别用于对第一和第二电容器进行预充电，以减少直流建立时间。

公开(公告)号：US06404780B1

公开(公告)日：2002-06-11

申请号：US09219775

申请日：1998-12-23

申请人： Donald Raymond Laturell ,  Lane A. Smith ,  Tony S. El-kik

发明人： Donald Raymond Laturell ,  Lane A. Smith ,  Tony S. El-kik

IPC分类号： H04J306

CPC分类号： H04J3/0608 ,  H04B14/04

摘要： The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream. An interrupt is sent to the slave device by withholding the data clock signal for a predetermined amount of time. Upon receipt of the interrupt, the slave device monitors the data stream for the presence of the preamble code word. Upon detection of the preamble code word, data transmitted by the codec is again enabled.

摘要翻译： 本发明提供一种同步数据协议，其包括一个或多个串行输入输出（SIO）控制字和跨越高电压接口的数据，以允许消除帧同步信号（和相应的AC耦合电容）。 本发明对于一般的时分多路复用（TDM）数据，串行数据通信设备或同步串行通信接口以及音频编解码器设备中的控制器与编解码器之间的通信具有特别的适用性， AC '97规格，即AC Link。 通过发送数据信号线实现同步数据协议，以在两个通信设备之间提供偶尔的同步（即，不是逐帧同步）。 主设备包括前导码插入模块，用于将预定的前导码字插入到发送的数据流中。 通过在数据时钟信号中保持预定的时间量将中断发送到从设备。 在接收到中断时，从设备监视数据流以存在前导码字。 在检测到前导码字时，再次启用由编解码器发送的数据。

公开(公告)号：US08861580B2

公开(公告)日：2014-10-14

申请号：US11434687

申请日：2006-05-16

申请人： Christopher J. Abel ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith

发明人： Christopher J. Abel ,  Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith

IPC分类号： H03H7/30 ,  H04L25/03 ,  H04L1/20

CPC分类号： H04L25/03343 ,  H04L1/205 ,  H04L2025/03681 ,  H04L2025/03802

摘要： Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

摘要翻译： 提供了用于基于数据眼睛监测来确定一个或多个信道补偿参数的方法和装置。 根据本发明的一个方面，提供了一种用于评估与信号相关联的数据眼的质量的方法。 对于多个不同的相位，例如使用至少两个锁存器对接收到的信号进行采样，并且评估采样以识别信号何时跨越预定义的幅度值，例如零交叉。 确定预定义的幅度交叉点是否满足一个或多个预定标准。 一个或多个信道补偿技术的一个或多个参数可以根据确定步骤的结果来任意地进行调整。 也可以根据确定步骤的结果，调整相邻发射机的一个或多个参数以减少近端串扰。

公开(公告)号：US08798222B2

公开(公告)日：2014-08-05

申请号：US11095770

申请日：2005-03-31

申请人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

发明人： Mohammad S. Mobin ,  Gregory W. Sheets ,  Lane A. Smith ,  Craig B. Ziemer

IPC分类号： H04L7/00

CPC分类号： H03K5/13 ,  H03K2005/00052 ,  H04L7/00

摘要： Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.

摘要翻译： 提供了用于模拟相位内插器的数字线性化的方法和装置。 多达2N个所需的相位值被映射到对应的M位值，其中M大于N.相应的M位值被施加到相位内插器以获得期望的2N个期望相位值。 还提供了线性化相位内插器，其考虑过程，电压，温度或老化（PVTA）变化。

公开(公告)号：US20130282995A1

公开(公告)日：2013-10-24

申请号：US13449684

申请日：2012-04-18

申请人： Jung Ho Cho ,  Vladimir Sindalovsky ,  Lane A. Smith

发明人： Jung Ho Cho ,  Vladimir Sindalovsky ,  Lane A. Smith

IPC分类号： G06F12/02

CPC分类号： G06F1/12 ,  G06F5/065 ,  G06F5/14 ,  G06F2205/066

摘要： In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.

摘要翻译： 在所描述的实施例中，多个先入先出的缓冲指针（多FIFO指针）对准系统包括同步电路以对准多个FIFO缓冲器操作。 FIFO读时钟停止信号由主逻辑产生，停止所有发送通道共享的读时钟，然后重新启动读时钟对齐它们。 FIFO读时钟停止信号被施加到需要对齐的所有FIFO的读时钟上，并且当需要速率改变时，FIFO读时钟停止信号暂停读时钟，导致本地写指针和读指针被复位。 在FIFO读取时钟停止信号被取消断言之后，读取时钟同时开始到所有FIFO，从而对齐信道。

公开(公告)号：US08548038B2

公开(公告)日：2013-10-01

申请号：US13312443

申请日：2011-12-06

申请人： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith ,  Amaresh V. Malipatil ,  Pervez M. Aziz

发明人： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith ,  Amaresh V. Malipatil ,  Pervez M. Aziz

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/03636 ,  H04L2025/03694

摘要： In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

摘要翻译： 在所描述的实施例中，串行器解串器（SerDes）接收器包括模式检测器，其允许检测到不充分随机的模式周期和低活动期。 在这些时期内冻结均衡适应可能会通过将不合格的模式嵌入到适应数据中来实现。 一些实施例还允许检测长的冻结间隔，并且因此延迟冻结断言以便接收器的时钟和数据恢复（CDR）电路重新获得对串行数据的锁定。 在接收数据中嵌入冻结信息可以精确地同步接收数据并进行冻结。