摘要:
In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.
摘要:
Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.
摘要:
Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step
摘要:
Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.
摘要:
Methods and apparatus are provided fox equalizing a received signal. A received signal is equalized by determining a data rate of the received signal; obtaining one or more equalization parameters associated with the determined data rate; and equalizing the received signal using the obtained one or more equalization parameters. The equalization parameters may comprise, for example, one or more of a gain parameter, zero control for a high pass filter and one or more threshold settings for one or more latches used during the equalizing step, such as data latches or transition latches (or both).
摘要:
Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.
摘要:
Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要:
Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要:
A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
摘要:
Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization. A threshold position of a latch employed by a decision-feedback equalizer is determined by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; and determining a threshold position of the latch based on the samples. The constrained input data can comprise (i) transitions from a binary value of 1 to a binary value of 0 or 1; or (ii) transitions from a binary value of 0 to a binary value of 0 or 1. The size of the single-sided data eye can be obtained by analyzing a histogram associated with the single-sided data eye to identify a region having a constant hit count.