公开(公告)号：US20040046588A1

公开(公告)日：2004-03-11

申请号：US10242165

申请日：2002-09-11

发明人： Alexander Tetelbaum

IPC分类号： H03K019/177

CPC分类号： H04L25/242 ,  H01L23/5225 ,  H01L2924/0002 ,  H04L25/085 ,  H01L2924/00

摘要： A global interconnect distribution system is disclosed. The global interconnect distribution system includes a global interconnect cell capable of producing at least two substantially identical output signals, and a global interconnect coupled to the cell for carrying one of the output signals. At least one wire is also coupled to the cell that is routed adjacent to the global interconnect for carrying the other output signal to provide active shielding for the global interconnect, thereby increasing signal integrity and signal transmission of the global interconnect.

摘要翻译： 公开了全球互连分配系统。 全局互连分配系统包括能够产生至少两个基本上相同的输出信号的全局互连单元，以及耦合到该单元的用于承载输出信号之一的全局互连。 至少一根导线还耦合到相邻于全局互连的路由单元，用于承载另一个输出信号以为全局互连提供主动屏蔽，从而增加全局互连的信号完整性和信号传输。

公开(公告)号：US20030222676A1

公开(公告)日：2003-12-04

申请号：US10239133

申请日：2002-09-19

发明人： Richard M. Lienau

IPC分类号： H03K019/177

CPC分类号： H03K17/6871 ,  G11C7/22 ,  G11C11/15 ,  G11C2207/2227 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/1778

摘要： A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array.

摘要翻译： 一种可编程阵列逻辑电路，其临时存储器电路采用单位非易失性铁磁存储器单元。 铁磁存储器单元或位存储数据，即使没有电力提供给电路，从而在可编程逻辑电路的操作期间节省功率，并确保在暂时停电时不会丢失数据。 此外，铁磁单元提供对数据的不确定数量的切换动作，而不降低存储数据的能力。 本发明提供一种集成电路，包括其中具有产品线和输入线的可编程逻辑电路阵列和存储寄存器电路。 存储寄存器电路具有铁磁位和传感器，其耦合以存储剩余控制信号和输出晶体管，耦合以响应于其栅极上的剩余控制信号，并耦合在输入和产品线之间。 此外，集成电路还可以包括逻辑AND阵列和逻辑OR阵列。

公开(公告)号：US20030201794A1

公开(公告)日：2003-10-30

申请号：US10426991

申请日：2003-04-29

申请人： Altera Corporation

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K019/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of sub-regions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括可编程逻辑的多个区域，并且每个区域包括可编程逻辑的多个子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US20030201792A1

公开(公告)日：2003-10-30

申请号：US10411627

申请日：2003-04-11

申请人： Actel Corporation, a California Corporation

发明人： Reza Asayeh

IPC分类号： H03K019/177

CPC分类号： H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may be made larger with minimal changes to the architecture. Disposed along the edges of each repeatable block are bidirectional buffer banks for connecting to adjacent blocks and to an interconnect matrix that is connectable to blocks other than adjacent blocks. Disposed at regular intervals in the interconnect matrix are repeater buffers to limit the number of antifuses on a given track of the interconnect matrix, to minimize RC delay, and to avoid violating the Ipeak limit.

公开(公告)号：US20030179011A1

公开(公告)日：2003-09-25

申请号：US10103495

申请日：2002-03-20

发明人： Jon Goodbread ,  John Stanback ,  Chris Feng ,  Martha Johnson

IPC分类号： H03K019/177

CPC分类号： G11C17/165 ,  G11C17/16 ,  G11C2213/72 ,  H01L23/5256 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated polysilicon fuse and diode and methods of making the same are provided. The integrated polysilicon fuse and diode combination may be implemented in a programmable cross point fuse array. The integrated polysilicon fuse and diode may be used in a random access memory (RAM) cell. The polysilicon diode may be isolated from a substrate and other devices, use less area on a substrate, and cost less to manufacture compared to other diodes.

摘要翻译： 提供集成多晶硅熔丝和二极管及其制造方法。 集成多晶硅熔丝和二极管组合可以在可编程交叉点熔丝阵列中实现。 集成多晶硅保险丝和二极管可以用在随机存取存储器（RAM）单元中。 多晶硅二极管可以与衬底和其他器件隔离，在衬底上使用较少的面积，并且与其它二极管相比成本较低。

公开(公告)号：US20030128051A1

公开(公告)日：2003-07-10

申请号：US10361477

申请日：2003-02-06

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  David Edward Jefferson ,  Rina Raman ,  L. Todd Cope ,  Christopher F. Lane ,  Joseph Huang ,  Francis B. Heile ,  Bruce B. Pedersen ,  David Wolk Mendel ,  Craig Schilling Lytle ,  Robert Richard Noel Bielby ,  Kerry Veenstra

IPC分类号： H03K019/177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

公开(公告)号：US20030076130A1

公开(公告)日：2003-04-24

申请号：US10170026

申请日：2002-06-10

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K019/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

公开(公告)号：US20030052712A1

公开(公告)日：2003-03-20

申请号：US10190003

申请日：2002-07-05

发明人： Alan Elbert Comer

IPC分类号： G06F007/38 ,  H03K019/173 ,  H01L027/10 ,  H01L029/00 ,  H03K019/177 ,  H01L025/00

CPC分类号： H03K19/17736 ,  H01L23/5252 ,  H01L23/5256 ,  H01L23/5382 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K19/1778 ,  H01L2924/00

摘要： Ladder network 396 comprises control terminals including at least ground terminal 50e and master terminal 60e, and slave terminals 51, 53, 55, 57, 59, each individually connected to terminal 50e through fuse elements 12a,b,c,d,e, respectively. Said slave terminals are also sequentially linked, each to the next through antifuses 42a,b,c,d, respectively. Master terminal 60e is connected to terminal 51. By applying programming signals to said control terminals, terminal 60e may be disconnected from terminal 50c and sequentially connected to each slave terminal. Described ladder variations include segmented ladder 400, wherein terminal 60e can be sequentially connected to, and subsequently disconnected from, second conductors 51a,53a,55a,57a,59a; hierarchical ladder network 4000; and programmable SAW transducer 2000. Finally, a programmable architecture based upon such ladder networks, suitable for incorporation within a configurable IC package, is described, including also a programmable contact structure 300 if the package is stackable.

摘要翻译： 梯形网络396包括至少包括接地端子50e和主端子60e的控制端子以及分别通过熔丝元件12a，b，c，d，e连接到端子50e的从端子51,53,55,57,59。 。 所述从属终端也分别依次通过反熔丝42a，b，c，d连接到下一个终端。 主端子60e连接到端子51.通过向所述控制端子施加编程信号，端子60e可以与端子50c断开并且顺序地连接到每个从属端子。 描述的梯子变化包括分段梯形物400，其中端子60e可以顺序地连接到第二导体51a，53a，55a，57a，59a并随后从第二导体51a，53a，55a，57a，59a断开; 分层梯形网络4000; 并且可编程SAW传感器2000.最后，描述了适于并入可配置IC封装内的基于这种梯形网络的可编程架构，如果封装是可堆叠的，还包括可编程触点结构300。

公开(公告)号：US20030001614A1

公开(公告)日：2003-01-02

申请号：US10186346

申请日：2002-06-28

申请人： STMicroelectronics Pvt. Ltd.

发明人： Moninder Singh ,  Anurag Chaudhry

IPC分类号： H03K019/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： A field programmable logic device includes at least two independently configurable embedded memory structures. The memory structures may differ in at least one parameter, such as memory size, available configuration depths, and available configuration widths. As such, a more efficient memory utilization is provided.

摘要翻译： 现场可编程逻辑器件包括至少两个可独立配置的嵌入式存储器结构。 存储器结构在至少一个参数中可能不同，例如存储器大小，可用配置深度和可用配置宽度。 因此，提供了更有效的存储器利用。

公开(公告)号：US20020163357A1

公开(公告)日：2002-11-07

申请号：US10117875

申请日：2002-04-05

申请人： BTR, Inc.

发明人： Benjamin S. Ting

IPC分类号： H03K019/177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

摘要： An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.

摘要翻译： 用于现场可编程门阵列（FPGA）的架构和分布式分层互连方案。 FPGA由多个对输入信号执行逻辑功能的单元组成。 可编程的内连接将属于逻辑集群的小区的每个输出之间的连接性提供给属于该逻辑集群的每个其他小区的至少一个输入。 一组可编程块连接器用于提供单元的逻辑簇之间的可连接性以及对分层路由网络的可访问性。 使用均匀分布的第一层路由网络线路来提供块连接器组之间的连接。 实现均匀分布的第二层路由网络线路以提供不同第一层路由网络线路之间的可连接性。 交换网络用于提供块连接器与对应于第一层的路由网络线路之间的可连接性。 其他交换网络提供对应于第一层的路由网络线路与对应于第二层的路由网络线路之间的可连接性。 实现了额外的均匀分布的路由网络线路层以提供不同的现有路由网络线路之间的可连接性。 当单元的数量作为阵列中的两个先前单元计数的平方函数增加时，添加另外的路由层，而路由线的长度和路由线的数量增加为两个的线性函数。 可编程双向passgates用作开关，用于控制要连接的路由网络线路。