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公开(公告)号：US3636867A
公开(公告)日：1972-01-25
申请号：US3636867D
申请日：1970-06-25
发明人： BONZANO GIORGIO
CPC分类号： G06K15/06
摘要： A high-speed ''''on-the-fly'''' printer, wherein timing means is provided to identify the position of the print characters on a movable type-carrying member, to denote the instant for actuation of the print operation, and to control the speed of the motor driving the type-carrying member.
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公开(公告)号：US3629621A
公开(公告)日：1971-12-21
申请号：US3629621D
申请日：1969-10-22
发明人： GENUIT LUTHER L
摘要： A bistable multivibrator employs a single transistor, a capacitor, a pair of four-layer diodes and a pair of transistors. Trigger pulses applied to the base of the transistor caused the multivibrator to be switched each time a positive pulse is applied.
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公开(公告)号：US3624483A
公开(公告)日：1971-11-30
申请号：US3624483D
申请日：1970-08-24
发明人： GENUIT LUTHER L
CPC分类号： H02M7/525 , H02M3/3155
摘要： A pair of silicon-controlled rectifiers, a center tapped inductor, a pair of commutating capacitors, a transformer, and a pair of low-voltage diodes convert a relatively large value of unregulated DC voltage to a relatively small value of regulated DC voltage. A pair of conventional diodes connected across the commutating capacitors limit the reverse voltage across these capacitors and limit the operating currents and voltages in the other elements of the switching regulator.
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114.发明授权
公开(公告)号：US3610905A
公开(公告)日：1971-10-05
申请号：US3610905D
申请日：1965-04-15
发明人： HERRON EDWIN W , HUNTER ROBERT D , KEEFER DAVID E
CPC分类号： G06F7/535 , G06F7/4917
摘要： Division apparatus in a data processing system includes the selection of a number of quotient characters to be formed and employs operating registers of the data processing system. The most significant characters of the dividend and the divisor are used to develop a trial quotient and the trial quotient is used with the rest of the characters to obtain the actual quotient and remainder.
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115.发明授权Instructions to load and store containing words in a computer system emulator with host word size larger than that of emulated machine 有权在计算机系统仿真器中加载和存储包含字词的指令，其主机字大小于仿真机的大小公开(公告)号：US07406406B2
公开(公告)日：2008-07-29
申请号：US11006414
申请日：2004-12-07
CPC分类号： G06F9/30043 , G06F9/30101 , G06F9/30174
摘要： Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine. A “LOAD64” instruction loads the emulator memory location representing an emulated “Q” (supplementary accumulator) register with the “normal” 36-bits of the containing word. At the same time, the “upper” 28 bits of the 64-bit containing word is copied into the emulator memory location representing an emulated “A” (accumulator) register. Thus, the emulated 36-bit machine “sees” and can examine the 64-bit word in its entirety. A “Store64” instruction stores the emulated “Q” register contents into the lower 36-bits of the 64-bit containing word, and at the same time stores the lower 28 bits of the emulated “A” register contents into the upper 28 bits of the 64-bit containing word.
摘要翻译： 提供了用于在主机64位机器上仿真的目标36位机器的指令集的两个唯一指令，以便实现模拟应用程序对存储在存储器中的“包含”字的可见性 主机。 “LOAD64”指令将模拟器存储位置加载到包含字的“正常”36位的模拟“Q”（补充累加器）寄存器中。 同时，64位包含字的“上”28位被复制到表示仿真“A”（累加器）寄存器的仿真器存储单元中。 因此，仿真的36位机器“看到”并且可以检查64位字的整体。 “Store64”指令将模拟的“Q”寄存器内容存储到64位包含字的低36位，同时将仿真的“A”寄存器内容的低28位存储到高位28位 的64位包含字。
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116.发明授权Associative memory system with a multi-digit incrementable validity counter 有权具有多位可递增有效性计数器的关联存储器系统公开(公告)号：US06938145B2
公开(公告)日：2005-08-30
申请号：US10309459
申请日：2002-12-04
CPC分类号： G06F12/1027
摘要： A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter. If there is a full match, a switch issues the real page address read from the associative memory entry. If there is not a match, the page table is consulted to obtain the real address of the requested page, and the associative memory is updated accordingly.
摘要翻译： 计算机系统包括中央处理单元，存储数据页和页表的可寻址主存储器和关联存储器。 关联存储器根据当CPU处理器发出的低阶虚拟地址组件访问主存储器中的给定页面时存储多个条目。 关联存储器中的每个条目包括分别保持：1）高阶虚拟地址分量的字段; 2）真实页面地址; 和3）多位数有效性计数。 CPU中可增量的多位计数器存储当前的有效性计数。 当寻求访问数据页时，比较器接收：1）数据页的高阶虚拟地址分量; 2）从关联存储器条目读取的高阶虚拟地址组件; 3）从关联存储器条目读取的多位数有效性计数; 和4）计数器中的多位数的当前有效性计数。 如果完全匹配，则交换机会发出从关联内存条目读取的真实页面地址。 如果没有匹配，则查询页表以获得所请求页面的真实地址，并且相关联的存储器被相应地更新。
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117.发明授权Method and data processing system for performing atomic multiple word reads 有权用于执行原子多重字读取的方法和数据处理系统公开(公告)号：US06922666B2
公开(公告)日：2005-07-26
申请号：US09746792
申请日：2000-12-22
申请人： Bruce A. Noyes
发明人： Bruce A. Noyes
IPC分类号： G06F9/455
CPC分类号： G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found unlocked. Check speculation instructions are utilized after the gate flag tests to verify that the corresponding cache lines have not been invalidated through a write by another processor since the speculative loads were issued. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.
摘要翻译： 当在不支持原子多重字读取的主机系统上模拟目标系统时，提供了原子多字读取。 除了要读取的最后一个字之外，还将使用高级推测负载读取门标志，并进行测试，直到找到解锁。 在门标志测试之后，检查猜测指令是否被用于验证相应的高速缓存行是否已经由另一个处理器的写入而无效，因为发布了推测负载。 在具有比目标系统更长的字大小的主机系统中，门标志可以存储在主机系统字中的另外未使用的位中，其中包含要写入的目标系统字。
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118.发明授权Rebuilding “in-doubt” states reliably after multiple system failures in a data processing system performing two-phase transaction processing 有权在执行两阶段事务处理的数据处理系统中多次系统故障后，重建“无疑”状态可靠公开(公告)号：US06895529B2
公开(公告)日：2005-05-17
申请号：US10075309
申请日：2002-02-13
申请人： David A. Egolf , Eric W. Hardesty
发明人： David A. Egolf , Eric W. Hardesty
CPC分类号： G06F11/1474 , G06F11/1441 , G06F2201/80 , G06F2201/825
摘要： A data processing system participating in two-phase transaction processing operations which, when a system failure occurs while one or more transactions are in process, can successfully rebuild “in-doubt” states even when another system failure occurs during an attempt to effect the rebuild. The system includes a file management system having exclusive access to reserved locations in the memory for reading and writing meta-data therein and physical file access logic selectively coupling the memory and the database access application, the physical file access logic incorporating file protections which are controlled by the file management system; such that, in the event of a failure, the local state of the transaction can be faithfully rebuilt after restart by accessing the meta-data. Upon restart after a failure, the results of incomplete non-“in-doubt” transactions are removed, the files which have been updated by “in-doubt” transactions are locked and normal access to the affected database is then permitted.
摘要翻译： 参与两阶段事务处理操作的数据处理系统，当在一个或多个事务处理期间发生系统故障时，即使在尝试执行重建期间发生另一个系统故障时，也可以成功地重建“无疑”状态 。 该系统包括文件管理系统，其具有对存储器中用于读取和写入元数据的预留位置的独占访问，以及选择性地耦合存储器和数据库访问应用的物理文件访问逻辑，所述物理文件访问逻辑包含被控制的文件保护 由文件管理系统; 使得在发生故障的情况下，可以通过访问元数据来重新启动交易的本地状态。 失败后重新启动，不完整的非“无疑”事务的结果将被删除，已经被“无疑”事务更新的文件被锁定，然后允许对受影响的数据库进行正常访问。
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119.发明申请Method and data processing system providing data conversion across multiple heterogeneous computer systems 审中-公开方法和数据处理系统提供跨多个异构计算机系统的数据转换公开(公告)号：US20030140170A1
公开(公告)日：2003-07-24
申请号：US09896699
申请日：2001-06-29
IPC分类号： G06F015/16
摘要： Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.
摘要翻译： 批量数据由第一计算机系统上的应用程序读取或写入第二异构计算机系统上的文件。 或者，它在这些异构系统上的应用程序之间直接读取或写入批量数据。 作业或任务从一个系统启动到在第二个异构系统上执行。 然后将结果返回到第一个系统。 还从第一个系统启动检查点和以后重新启动，以在第二个异构系统上执行。
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120.发明申请Method and data processing system for performing atomic multiple word reads 有权用于执行原子多重字读取的方法和数据处理系统公开(公告)号：US20020082822A1
公开(公告)日：2002-06-27
申请号：US09746792
申请日：2000-12-22
发明人： Bruce A. Noyes
IPC分类号： G06F009/455
CPC分类号： G06F9/45554 , G06F9/45558 , G06F2009/45583
摘要： Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found unlocked. Check speculation instructions are utilized after the gate flag tests to verify that the corresponding cache lines have not been invalidated through a write by another processor since the speculative loads were issued. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.
摘要翻译： 当在不支持原子多重字读取的主机系统上模拟目标系统时，提供了原子多字读取。 除了要读取的最后一个字之外，还将使用高级推测负载读取门标志，并进行测试，直到找到解锁。 在门标志测试之后，检查猜测指令是否被用于验证相应的高速缓存行是否已经由另一个处理器的写入而无效，因为发布了推测负载。 在具有比目标系统更长的字大小的主机系统中，门标志可以存储在主机系统字中的另外未使用的位中，其中包含要写入的目标系统字。
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