公开(公告)号：US06906587B2

公开(公告)日：2005-06-14

申请号：US10355859

申请日：2003-01-31

Applicant: Klaas Wortel

Inventor： Klaas Wortel

IPC: H03F3/45

CPC classification number: H03F3/45237

Abstract: An amplifier circuit. In one embodiment, the amplifier includes a first pair of transistors and a second pair of transistors. Each transistor in the amplifier includes a control terminal (e.g. a gate) as well as a first and second terminals. In one embodiment, the transistors are field effect transistors (FETs) and thus the first and second terminals may be either source or drain terminals. First terminals of each of the first pair of transistors may be coupled to a voltage source. The first terminal of each of the second pair of transistors is coupled to the second terminal of one of the first pair of transistors. A current source may be coupled between each of the second terminals and a voltage reference (e.g. ground plane).

Abstract translation: 放大器电路。 在一个实施例中，放大器包括第一对晶体管和第二对晶体管。 放大器中的每个晶体管包括控制端（例如栅极）以及第一和第二端子。 在一个实施例中，晶体管是场效应晶体管（FET），因此第一和第二端子可以是源极或漏极端子。 第一对晶体管中的每一个的第一端子可以耦合到电压源。 第二对晶体管中的每一个的第一端耦合到第一对晶体管之一的第二端。 电流源可以耦合在每个第二端子和电压参考（例如接地平面）之间。

公开(公告)号：US06868468B2

公开(公告)日：2005-03-15

申请号：US10076105

申请日：2002-02-14

Applicant: Richard H. Boz ,  Ronald W. Streiber ,  John D. Virzi ,  Richard E. Wahler

Inventor： Richard H. Boz ,  Ronald W. Streiber ,  John D. Virzi ,  Richard E. Wahler

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/14 ,  G06F13/40

CPC classification number: G06F13/4081

Abstract: A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.

Abstract translation: 公开了用于热对接的方法和装置。 在一个实施例中，便携式计算机系统包括总线桥和耦合到总线桥的总线。 总线可以具有耦合到其的一个或多个外围设备或外围接口。 总线也可以耦合到具有总线开关的对接接口。 总线开关在闭合并且计算机耦合到对接站时可将总线耦合到对接站中的外围接口。 总线开关可以响应于对接而关闭，从而完成总线到对接站中的外围接口的电耦合。 总线开关的关闭可以由对接接口控制，使得总线上的操作在对接过程期间不被中断。

公开(公告)号：US06838942B1

公开(公告)日：2005-01-04

申请号：US10622051

申请日：2003-07-17

Applicant: Thomas A. Somerville ,  Klaas Wortel

Inventor： Thomas A. Somerville ,  Klaas Wortel

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/72 ,  H03F3/04

CPC classification number: H03F1/025 ,  H03F3/211 ,  H03F3/72

Abstract: Various embodiments of methods and apparatus for an amplifier with wide output voltage swing are disclosed. The amplifier may include multiple output stages, each associated with a distinct supply voltage. Each output stage may contribute current to the output of the amplifier over a range of amplifier output voltages and these ranges may overlap. Each output stage may contribute current until the amplifier output voltage reaches the supply voltage associated with that output stage. The amplifier output may be as great as the largest supply voltage minus a drop equal to Rdson for an output transistor multiplied by the output current. In a CMOS implementation, this voltage drop may be approximately 0.15V. When the amplifier output voltage is close to the supply voltage associated with an output stage, both that output stage and the output stage associated with the next highest supply voltage may contribute to the amplifier output.

Abstract translation: 公开了具有宽输出电压摆幅的放大器的方法和装置的各种实施例。 放大器可以包括多个输出级，每个输出级与不同的电源电压相关联。 每个输出级可以在放大器输出电压的范围内向放大器的输出提供电流，并且这些范围可以重叠。 每个输出级可以贡献电流，直到放大器输出电压达到与该输出级相关联的电源电压。 放大器输出可能与最大电源电压减去等于输出晶体管的输出电流的Rdson相等的输出电流。 在CMOS实现中，该电压降可以是大约0.15V。 当放大器输出电压接近与输出级相关的电源电压时，与下一个最高电源电压相关的输出级和输出级均可能有助于放大器输出。

公开(公告)号：US5612648A

公开(公告)日：1997-03-18

申请号：US403931

申请日：1995-03-14

Applicant: Kelly P. McClellan ,  Parameswaran K. Gopalier ,  Khosrow H. Sadeghi

Inventor： Kelly P. McClellan ,  Parameswaran K. Gopalier ,  Khosrow H. Sadeghi

IPC: H03F3/45 ,  H03H11/04 ,  H03F3/191

CPC classification number: H03F3/45197 ,  H03F3/45179 ,  H03F2203/45466 ,  H03F2203/45471 ,  H03H11/0422

Abstract: A G.sub.m -C filter is formed using transconductor elements having first and second degeneration FETs to which first and second control signals are applied. A phase-locked-loop is used to generate the control signals. The control range of the transconductor elements is increased so that the frequency response of the filter can be maintained over increased ranges of various parameters (e.g., supply voltage variations, temperature variations, etc.)

Abstract translation: 使用具有施加第一和第二控制信号的第一和第二退化FET的跨导元件形成Gm-C滤波器。 锁相环用于产生控制信号。 跨导元件的控制范围增加，使得可以在各种参数的增加的范围（例如，电源电压变化，温度变化等）上保持滤波器的频率响应。

公开(公告)号：US5602995A

公开(公告)日：1997-02-11

申请号：US242496

申请日：1994-05-13

Applicant: Ariel Hendel ,  Kenneth W. Brinkerhoff

Inventor： Ariel Hendel ,  Kenneth W. Brinkerhoff

IPC: G06F13/00 ,  G06F5/06 ,  G06F12/02 ,  H04L12/56 ,  H04L29/06

CPC classification number: H04L29/06 ,  G06F12/0223 ,  G06F5/06 ,  H04L49/90

Abstract: Method and apparatus for buffering data packets in a data communication controller environment. In general, the communication controller is interfaceable with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a unique packet number. Packet number assignment is carried out by a memory management unit which dynamically allocates to each assigned packet number, one or more pages in data packet buffer memory for the storage of the corresponding data packet. If requested storage space is unavailable at the time of request, the memory management unit will allocate a page or pages to an available packet number as the pages become free. Upon issuing the assigned packet number, the physical addresses of the allocated pages of buffer memory storage space are generated in a manner transparent to both the host processor and the control unit. With these physical addresses, a data packet can be accessed from buffer memory, in a simple manner. Upon completion of each data packet loading operation, the corresponding packet number is stored in a packet number queue maintained for subsequent retrieval in order to generate the physical addresses at which the corresponding data packet has been stored.

Abstract translation: 用于在数据通信控制器环境中缓冲数据分组的方法和装置。 通常，通信控制器可与主处理器接口，并且包括用于访问通信介质的控制单元。 要发送或接收的每个数据分组被分配唯一的分组号。 分组编号分配由动态分配给每个分配的分组号的数据分组缓冲存储器中的一个或多个页面用于存储对应的数据分组的存储器管理单元执行。 如果所请求的存储空间在请求时不可用，则内存管理单元将在页面空闲时将页面或页面分配给可用的分组号。 在发布分配的分组号时，以对主机处理器和控制单元都是透明的方式生成分配的缓冲存储器存储空间的页面的物理地址。 利用这些物理地址，可以以简单的方式从缓冲存储器访问数据包。 在完成每个数据分组加载操作时，相应的分组号被存储在保持为后续检索的分组号队列中，以便生成相应数据分组被存储的物理地址。

公开(公告)号：US5191655A

公开(公告)日：1993-03-02

申请号：US782911

申请日：1991-10-24

Applicant: Haig Sarkissian

Inventor： Haig Sarkissian

IPC: G06F13/38

CPC classification number: G06F13/38

Abstract: An interface circuit is described for use with a plurality of peripherals or attachments connected in data communication with a central computer. The computer sends data messages, each of which includes the unique addresses of that peripheral to which the particular data message is directed. The peripheral interface contains areas for stripping and then storing addresses from the message received from the computer. If the address matches that of the peripheral, the peripheral acts on the message and responds when necessary to the computer with a message return that includes the address.

Abstract translation: 描述了一种接口电路，用于与中央计算机进行数据通信连接的多个外围设备或附件。 计算机发送数据消息，每个数据消息包括特定数据消息所指向的该外设的唯一地址。 外设接口包含剥离的区域，然后存储从计算机接收的消息中的地址。 如果地址与外设匹配，则外设将对消息进行操作，并在需要时使用包含地址的消息返回给计算机进行响应。

公开(公告)号：US5168176A

公开(公告)日：1992-12-01

申请号：US734554

申请日：1991-07-23

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K19/003

CPC classification number: H03K19/00361

Abstract: A method of controlling the ill-effects of ground bounce in a CMOS device, according to the present invention, comprises increasing the impedance between (1) the output line of a quiescent channel that is already at a low state, and (2) the local ground within the CMOS device; the increased impedance occurring when a ground bounce condition caused by an adjacent channel within the CMOS device would otherwise cause the output of the quiescent channel to be dragged high.

Abstract translation: 根据本发明的控制CMOS器件中的接地反弹的不良影响的方法包括增加（1）已经处于低状态的静态通道的输出线之间的阻抗和（2） CMOS设备内的本地接地; 当由CMOS器件中的相邻通道引起的接地反弹条件将导致静态通道的输出被拖拽高时发生的增加的阻抗发生。

公开(公告)号：US4824803A

公开(公告)日：1989-04-25

申请号：US064501

申请日：1987-06-22

Applicant: Natasha Us ,  Bonggi Kim ,  John E. Berg

Inventor： Natasha Us ,  Bonggi Kim ,  John E. Berg

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L23/53223 ,  H01L21/76886 ,  H01L2924/0002

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are fabricated through the deposition of a sandwich structure of metal. The bottom layer of a refractory metal prevents aluminum spiking into silicon; the top layer of refractory metal or alloy serves to reduce hillocking of the middle layer of conductive material. The upper layer of refractory metal at the location of the contact pads is etched off to improve bonding during packaging.

Abstract translation: 用于半导体集成电路的金属触点和互连通过沉积金属夹层结构来制造。 难熔金属的底层防止铝掺入硅中; 难熔金属或合金的顶层用于减少中间层导电材料的小丘。 蚀刻掉接触垫位置处的难熔金属上层，以改善包装过程中的粘结。

公开(公告)号：US4538113A

公开(公告)日：1985-08-27

申请号：US597264

申请日：1984-04-06

Applicant: Charles A. Lish

Inventor： Charles A. Lish

IPC: H03H19/00 ,  H03F3/68

CPC classification number: H03H19/004

Abstract: A band-pass filter includes an arrangement of individual filter sections and means for weighting and summing the band-pass functions of the filter sections such that the active conjugate pole pairs are arranged in the z plane on a circle concentric to the unit circle and spaced by equal angles with the exception of corrector poles, which are spaced by half-angle increments from the adjacent poles. In the embodiment of the invention described, the filter sections are in the form of digitally controlled switched capacitor filters.

Abstract translation: 带通滤波器包括单个滤波器部分的布置以及用于对滤波器部分的带通功能进行加权和求和的装置，使得有源共轭极对在z平面上以与单位圆同心的圆上排列并且间隔开 除了与相邻极间隔开半角增量的校正极之外，角度相等。 在所描述的本发明的实施例中，滤波器部分是数字控制的开关电容滤波器的形式。

公开(公告)号：US4394751A

公开(公告)日：1983-07-19

申请号：US200085

申请日：1980-10-23

Applicant: Steve Burstein ,  Jay Popper

Inventor： Steve Burstein ,  Jay Popper

IPC: G11C11/413 ,  G11C7/00

CPC classification number: G11C11/413

Abstract: A low power storage cell includes a flip-flop circuit along with associated circuitry to place the flip-flop in an access mode for reading data and in a storage mode when the flip-flop is not being accessed. In the storage mode the flip-flop stores data at very low voltage and current levels, thus greatly reducing power consumption. Reduced power consumption in the storage mode permits the device to retain data for long periods of time, in the event of power failure, with minimal backup power supply capacity.

Abstract translation: 低功率存储单元包括触发器电路以及相关联的电路，以将触发器置于用于读取数据的存取模式和当触发器未被访问时的存储模式。 在存储模式下，触发器将数据存储在非常低的电压和电流水平，从而大大降低功耗。 在存储模式下降低功耗允许设备在电源故障的情况下长时间保留数据，备用电源容量最小。