公开(公告)号：US5981326A

公开(公告)日：1999-11-09

申请号：US46243

申请日：1998-03-23

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/765 ,  H01L21/8238

CPC classification number: H01L21/765 ,  H01L21/761 ,  H01L21/762 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117

Abstract: This invention is a processing method for electrically isolating CMOS transistors. The method involves implanting a channel stop dopant into field regions between transistor active regions, self aligning relatively thick silicon dioxide over these field regions and providing thin oxide in the active regions that are self aligned to the field regions. The method does not require any shallow trench isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

Abstract translation: 本发明是用于电绝缘CMOS晶体管的处理方法。 该方法包括将沟道阻挡掺杂剂注入到晶体管有源区域之间的场区域中，在这些场区域上自对准相对较厚的二氧化硅，并在与场区域自对准的有源区域中提供薄氧化物。 该方法不需要任何浅沟槽隔离（STI），并且不需要局部氧化硅（LOCOS），从而导致对硅的损害很小。

公开(公告)号：US5970367A

公开(公告)日：1999-10-19

申请号：US942323

申请日：1997-10-01

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/00

CPC classification number: H01L29/66772 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667

Abstract: The present invention is a technique for producing silicon-on-insulator MOS transistors by damascene patterning of source-drain regions in a thin film of amorphous silicon deposited on a layer of oxide grown on a silicon wafer, where the oxide has previously been etched with a pattern of trenches. In addition, the technique provides for the amorphous layer to contact the underlying silicon substrate through multiple small oxide openings; where these openings have been previously filled with amorphous silicon, planarized and annealed at high temperature to form single crystal silicon; and where subsequent transistor channel regions will align to these filled openings. After patterning, the wafer is annealed in a second high temperature cycle, where the regions of amorphous silicon in contact with the single crystal silicon in the openings will convert into single crystal silicon suitable for transistor channel regions.

Abstract translation: 本发明是通过在沉积在硅晶片上生长的氧化物层上的非晶硅薄膜中的源极 - 漏极区域进行镶嵌图案化来制造绝缘体上硅MOS晶体管的技术，其中氧化物已经预先用 一种沟通模式。 此外，该技术提供非晶层通过多个小的氧化物开口接触下面的硅衬底; 其中这些开口预先填充有非晶硅，在高温下进行平面化和退火以形成单晶硅; 并且其中随后的晶体管沟道区域将与这些填充的开口对准。 在图案化之后，晶片在第二高温循环中退火，其中与开口中的单晶硅接触的非晶硅的区域将转换成适用于晶体管沟道区的单晶硅。

公开(公告)号：US06228716B1

公开(公告)日：2001-05-08

申请号：US09442896

申请日：1999-11-18

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L218247

CPC classification number: H01L27/11521

Abstract: This invention is a processing method for forming flash memory MOS transistors. The method uses chemical mechanical polishing to self align both a floating gate and an overlying control gate to the MOS channel region in both the width and length directions, thereby improving layout density. The method enables the capacitance between the control gate and the floating gate to be much larger than the capacitance between the floating gate and the channel; this reduces programing voltages. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon.

Abstract translation: 本发明是用于形成闪存MOS晶体管的处理方法。 该方法使用化学机械抛光来将浮动栅极和上覆控制栅极在宽度和长度方向上自对准到MOS沟道区域，从而提高布局密度。 该方法使得控制栅极和浮置栅极之间的电容远大于浮置栅极和沟道之间的电容; 这降低了编程电压。 该方法不需要任何浅沟槽隔离（STI），并且不需要局部氧化硅（LOCOS），从而导致硅损坏很小。

公开(公告)号：US6015727A

公开(公告)日：2000-01-18

申请号：US93221

申请日：1998-06-08

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/285 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L29/66575 ,  H01L21/28512 ,  H01L21/32139 ,  H01L21/762 ,  H01L21/76895 ,  H01L23/485 ,  H01L21/3212 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002

Abstract: This invention is a processing method for forming MOS transistors. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to MOS gate electrodes directly over channel regions, and allows borderless connections to be made to source and drain regions, thereby improving layout density of small transistors. The method enables interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon. The method also prevents plasma damage of very thin gate dielectrics during processing.

Abstract translation: 本发明是一种用于形成MOS晶体管的处理方法。 该方法使用化学机械抛光来将MOS晶体管栅电极在宽度和长度方向上自由对准沟道区域。 该方法使得金属互连线能够直接在沟道区域上与MOS栅电极进行无边界连接，并且允许对源极和漏极区域进行无边界连接，从而改善小晶体管的布局密度。 该方法使得能够在平坦表面上图形化互连线，这有助于蚀刻非常窄且紧密间隔的线。 该方法不需要任何浅沟槽隔离（STI），并且不需要局部氧化硅（LOCOS），从而导致硅损坏很小。 该方法还可防止非常薄的栅极电介质在处理过程中的等离子体损伤。

公开(公告)号：US5891763A

公开(公告)日：1999-04-06

申请号：US955887

申请日：1997-10-22

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L21/00

CPC classification number: H01L21/28202 ,  H01L21/7624 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66636

Abstract: The present invention is a technique for producing planar silicon on insulator MOS transistors, where the channel regions are created in an underlying single crystal silicon wafer, and where the source-drain extension regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.

Abstract translation: 本发明是一种用于制造绝缘体上的平面硅MOS晶体管的技术，其中在下面的单晶硅晶片中形成沟道区，并且其中源极 - 漏极延伸区是通过镶嵌沉积在非晶硅上的非晶硅薄膜 沉积在硅晶片上的氧化物层。

公开(公告)号：US5882958A

公开(公告)日：1999-03-16

申请号：US948211

申请日：1997-10-09

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/20 ,  H01L21/336 ,  H01L27/12 ,  H01L29/06 ,  H01L21/00

CPC classification number: H01L29/66651 ,  H01L27/1203 ,  H01L29/0653 ,  H01L21/2022

Abstract: The present invention is a technique for producing silicon-on-insulator MOS transistors by damascene patterning of source-drain regions in a thin film of amorphous silicon deposited on a layer of oxide grown on a silicon wafer, where the oxide has previously been etched with a pattern of trenches. In addition, the technique provides for the amorphous layer to contact the underlying silicon substrate through multiple small oxide openings, where subsequent transistor channel regions will align to these openings. After patterning, the wafer is annealed in a high temperature cycle, where the regions of amorphous silicon in contact with the silicon substrate will grow into single crystal silicon suitable for transistor channel regions.

Abstract translation: 本发明是通过在沉积在硅晶片上生长的氧化物层上的非晶硅薄膜中的源极 - 漏极区域进行镶嵌图案化来制造绝缘体上硅MOS晶体管的技术，其中氧化物已经预先用 一种沟通模式。 此外，该技术提供了非晶层通过多个小的氧化物开口接触下面的硅衬底，其中随后的晶体管沟道区域将与这些开口对准。 在图案化之后，晶片在高温循环中退火，其中与硅衬底接触的非晶硅区域将生长成适用于晶体管沟道区的单晶硅。

公开(公告)号：US5216299A

公开(公告)日：1993-06-01

申请号：US835207

申请日：1992-02-13

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K19/0185 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356 ,  H03K19/003

CPC classification number: H03K3/356017 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356113

Abstract: A lower power, noise rejecting TTL-to-CMOS input buffer, without the use of a current consuming voltage reference, has the characteristic of recognizing a logic LOW as less than 0.8 volts and a logic HIGH as greater than 2.0 volts for DC TTL signals while drawing only leakage current from its Vcc power supply, and simultaneously possesses the characteristic of rejecting high-amplitude Vin noise. For an input signal rapidly rising from zero to three volts, the buffer output switches at an input signal level of approximately 2.5 volts; and for the input signal rapidly falling from 3 to zero volts, the buffer output switches at an input signal level of approximately 1.4 volts.

Abstract translation: 低功耗，噪声抑制的TTL至CMOS输入缓冲器，不使用电流消耗电压基准，具有将逻辑低电平识别为小于0.8伏的特性，并且对于DC TTL信号具有大于2.0伏特的逻辑高电平 同时从Vcc电源中只吸收漏电流，同时具有抑制高振幅Vin噪声的特点。 对于输入信号从零快速上升到三伏，缓冲器输出在大约2.5伏特的输入信号电平处切换; 并且对于输入信号从3伏快速下降至零伏特，缓冲器输出在大约1.4伏特的输入信号电平处切换。

公开(公告)号：US06339550B1

公开(公告)日：2002-01-15

申请号：US09222369

申请日：1998-12-29

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: G11C1604

CPC classification number: G11C5/005 ,  G11C11/404 ,  G11C11/4078 ,  G11C11/4099

Abstract: An alpha particle striking the cell of a DRAM bit can destroy stored charge, resulting in a single bit soft error. A DRAM architecture is described that circumvents this problem by storing every DRAM bit redundantly in two cells. If a stored charge is represented by a logic 1, then when reading a DRAM bit, if either of it's cells is storing charge then the bit is a logic 1. Only if both cells of a bit have no charge is the bit a logic 0.

Abstract translation: 撞击DRAM位单元的α粒子可能会破坏存储的电荷，导致单个位软错误。 描述了通过将每个DRAM位冗余地存储在两个单元中来规避这个问题的DRAM架构。 如果存储的电荷由逻辑1表示，则当读取DRAM位时，如果其中的任何一个存储单元正在存储电荷，则该位为逻辑1.只有当位的两个单元都没有电荷时，该位为逻辑0 。

公开(公告)号：US6090672A

公开(公告)日：2000-07-18

申请号：US120953

申请日：1998-07-22

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H01L21/28 ,  H01L21/336 ,  H01L23/485 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66575 ,  H01L21/28141 ,  H01L23/485 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/66659 ,  H01L29/4966 ,  H01L29/66545 ,  H01L2924/0002

Abstract: This invention is a damascene processing method for forming ultra short channel MOS transistors, where the channel length is not determined by photolithography. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the MOS channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to the MOS gate electrodes directly over channel regions, and allows borderless connections to be made to the MOS source and drain regions, thereby improving layout density of small transistors. The method uses metal for first level interconnect lines rather than polysilicon. The method enables the interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon substrate. The method also prevents plasma damage of very thin gate dielectrics during processing.

Abstract translation: 本发明是一种用于形成超短沟道MOS晶体管的镶嵌处理方法，其中通道长度不由光刻确定。 该方法使用化学机械抛光来将MOS晶体管栅电极在宽度和长度方向上自对准MOS沟道区。 该方法使得金属互连线能够直接通过沟道区域与MOS栅电极无边界连接，并且允许对MOS源极和漏极区进行无边界连接，从而改善小晶体管的布局密度。 该方法使用金属作为一级互连线而不是多晶硅。 该方法使互连线能够在平坦表面上被图案化，这有助于蚀刻非常狭窄和紧密间隔的线。 该方法不需要任何浅沟槽隔离（STI），并且不需要局部氧化硅（LOCOS），从而对硅衬底几乎没有损坏。 该方法还可防止非常薄的栅极电介质在处理过程中的等离子体损伤。

公开(公告)号：US5168176A

公开(公告)日：1992-12-01

申请号：US734554

申请日：1991-07-23

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K19/003

CPC classification number: H03K19/00361

Abstract: A method of controlling the ill-effects of ground bounce in a CMOS device, according to the present invention, comprises increasing the impedance between (1) the output line of a quiescent channel that is already at a low state, and (2) the local ground within the CMOS device; the increased impedance occurring when a ground bounce condition caused by an adjacent channel within the CMOS device would otherwise cause the output of the quiescent channel to be dragged high.

Abstract translation: 根据本发明的控制CMOS器件中的接地反弹的不良影响的方法包括增加（1）已经处于低状态的静态通道的输出线之间的阻抗和（2） CMOS设备内的本地接地; 当由CMOS器件中的相邻通道引起的接地反弹条件将导致静态通道的输出被拖拽高时发生的增加的阻抗发生。