公开(公告)号：US07144687B2

公开(公告)日：2006-12-05

申请号：US10880519

申请日：2004-07-01

Applicant: Hidehiko Fujisaki ,  Kinnosuke Satou ,  Osamu Takahashi

Inventor： Hidehiko Fujisaki ,  Kinnosuke Satou ,  Osamu Takahashi

IPC: G03F7/20 ,  G11B21/21

CPC classification number: G11B5/4833

Abstract: A step of forming an insulating resin layer 31 includes a process of forming the insulating resin layer 31 made of a photo-sensitive resin on a load beam or a flexure 11 and an exposing and developing process in which a photo-mask 32 having different light transmittance between a part corresponding to a part near a slider mounting part 22 and other parts is applied to the insulating resin layer 31, exposed and developed so that the thickness of the insulating resin layer 31 of the part near the slider mounting part 22 is smaller than the thickness of the insulating resin layer 31 of other parts.

Abstract translation: 形成绝缘树脂层31的步骤包括在负载梁或挠曲件11上形成由感光树脂制成的绝缘树脂层31和曝光和显影处理的工艺，其中具有不同光的光掩模32 将对应于滑块安装部22附近的部分的部分与其他部分之间的透射率施加到绝缘树脂层31，暴露和显影，使得靠近滑块安装部22的部分的绝缘树脂层31的厚度较小 比其他部分的绝缘树脂层31的厚度大。

公开(公告)号：US20060270173A1

公开(公告)日：2006-11-30

申请号：US11137234

申请日：2005-05-25

Applicant: Hiroshi Yoshihara ,  Sang Dhong ,  Osamu Takahashi ,  Takaaki Nakazato

Inventor： Hiroshi Yoshihara ,  Sang Dhong ,  Osamu Takahashi ,  Takaaki Nakazato

IPC: G06F1/00 ,  H01L21/8222 ,  H01L27/12

CPC classification number: H03K19/0016

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract translation: 方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字 电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

公开(公告)号：US20060179176A1

公开(公告)日：2006-08-10

申请号：US11050040

申请日：2005-02-03

Applicant: Sang Dhong ,  Brian Flachs ,  Harm Hofstee ,  Osamu Takahashi

Inventor： Sang Dhong ,  Brian Flachs ,  Harm Hofstee ,  Osamu Takahashi

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F13/1626 ,  G06F13/1663

Abstract: A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.

Abstract translation: 提出了一种具有组合线和字访问的存储器的处理器的系统和方法。 系统执行窄读/写存储器访问，并使用多路复用器和锁存器对同一存储体进行宽读/写存储器访问以指导数据。 该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。 在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。 通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

公开(公告)号：US20060101364A1

公开(公告)日：2006-05-11

申请号：US10965625

申请日：2004-10-14

Applicant: Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

Inventor： Sang Dhong ,  Hiroaki Murakami ,  Shohji Onishi ,  Osamu Takahashi

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F9/30141

Abstract: A method, an apparatus, and a computer program are provided for distributing data in a high speed processing unit. Traditionally, true readout data from multiport register files are inverted multiple times when transmitting the readout to data latches, located at multiple physical layers. The inversion of the readout data can be boost the signals and provide the proper true or complement data to the data latches. To reduce the number of inverters, the register files are configured to output true and complement signals. Therefore, power consumption and area are reduced with the elimination of the inverters.

Abstract translation: 提供了一种用于在高速处理单元中分配数据的方法，装置和计算机程序。 传统上，当将多个端口寄存器文件的真实读出数据发送到位于多个物理层的数据锁存器时，会反复多次。 读出数据的反转可以提升信号，并为数据锁存器提供适当的真实或补充数据。 为了减少逆变器的数量，寄存器文件被配置为输出真实和补码信号。 因此，随着逆变器的消除，功耗和面积减少。

公开(公告)号：US20060097751A1

公开(公告)日：2006-05-11

申请号：US10982018

申请日：2004-11-05

Applicant: Sang Dhong ,  Brian Flachs ,  Joel Silberman ,  Osamu Takahashi

Inventor： Sang Dhong ,  Brian Flachs ,  Joel Silberman ,  Osamu Takahashi

IPC: H03K19/177

CPC classification number: H03K19/1772

Abstract: A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.

Abstract translation: 公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。 第二逻辑阵列耦合到第一逻辑阵列。 输出锁存器耦合到第二逻辑阵列。

公开(公告)号：US20060095802A1

公开(公告)日：2006-05-04

申请号：US10976259

申请日：2004-10-28

Applicant: Sang Dhong ,  Joel Silberman ,  Osamu Takahashi ,  James Warnock ,  Dieter Wendel

Inventor： Sang Dhong ,  Joel Silberman ,  Osamu Takahashi ,  James Warnock ,  Dieter Wendel

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/325

Abstract: An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.

Abstract translation: 提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。 通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。 在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。 通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。 因此，扫描控制信号可以在功能模式下禁用扫描链。

公开(公告)号：US07031230B1

公开(公告)日：2006-04-18

申请号：US09674868

申请日：2000-03-08

Applicant: Eiichi Nagasaka ,  Osamu Takahashi

Inventor： Eiichi Nagasaka ,  Osamu Takahashi

IPC: G04B1/00

CPC classification number: G04B27/04 ,  G04C10/00

Abstract: A starter which applies a mechanical rotating force to a rotor of an electromagnetic converter, such as a power generator, for startup of the rotor. The starter includes a startup spring (60) having an engaging portion (63) engageable with a 6th pinion (11a) of a wheel train coupled to the power generator. In interlock with the operation of pulling out a crown, a reset lever (70) is operated to bias the startup spring for engagement with the 6th pinion. Thereafter, the startup spring is released from the biased state in interlock with the operation of pushing in the crown. The startup spring is returned to the original position due to its own spring force, whereupon a mechanical rotating force is applied to the pinion. Since the rotating force can be set by a resilient force of only the startup spring, a stable rotating force is applied to the rotor (12).

Abstract translation: 将机械旋转力施加到用于启动转子的诸如发电机的电磁转换器的转子的起动器。 启动器包括启动弹簧（60），该起动弹簧具有可与耦合到发电机的轮系的第六小齿轮（11a）接合的接合部分（63）。 在与拔出冠部的操作联动的情况下，复位杆（70）被操作以偏置起动弹簧以与第六小齿轮接合。 此后，启动弹簧与推入表冠的操作互锁地从偏置状态释放。 启动弹簧由于其自身的弹簧力而返回到原始位置，于是向小齿轮施加机械旋转力。 由于旋转力可以通过仅起动弹簧的弹力来设定，因此向转子（12）施加稳定的旋转力。

公开(公告)号：US06944310B2

公开(公告)日：2005-09-13

申请号：US10377782

申请日：2003-03-04

Applicant: Masanori Ito ,  Kunio Mitobe ,  Osamu Takahashi

Inventor： Masanori Ito ,  Kunio Mitobe ,  Osamu Takahashi

IPC: H04R9/04 ,  H04R7/12 ,  H04R7/20 ,  H04R9/02 ,  H04R9/06 ,  H04R1/02 ,  H04R7/00

CPC classification number: H04R9/06

Abstract: A speaker apparatus includes an elliptical-shaped or a round-edged rectangular-shaped vibration plate; an edge damper portion disposed on an outer peripheral edge portion of the vibration plate; a recessed portion formed between said vibration plate and said edge damper portion, having a caliber of a shape corresponding to the shape of said vibration plate; and an air core voice coil fitted into an interior of said recessed portion. The speaker apparatus further includes a frame for mounting said edge damper portion to support said vibration plate, having a stepped portion and a vertical wall portion; and an edge damper frame arranged on an outer periphery of said edge damper portion, having a support portion placed on the stepped portion and a rising portion being in contact with the vertical wall portion.

Abstract translation: 扬声器装置包括椭圆形或圆边矩形振动板; 设置在所述振动板的外周缘部的边缘阻尼部; 形成在所述振动板和所述边缘阻尼部分之间的凹部，其具有与所述振动板的形状对应的形状的口径; 以及安装在所述凹部的内部的空心音圈。 扬声器装置还包括一个用于安装所述边缘阻尼器部分以支撑所述振动板的框架，具有台阶部分和垂直壁部分; 以及边缘阻尼器框架，其布置在所述边缘阻尼器部分的外周上，具有放置在台阶部分上的支撑部分和与垂直壁部分接触的上升部分。

公开(公告)号：US20050190720A1

公开(公告)日：2005-09-01

申请号：US11040885

申请日：2005-01-21

Applicant: Motoharu Miyake ,  Hiroshi Inamura ,  Kazunori Yamamoto ,  Hideharu Suzuki ,  Osamu Takahashi

Inventor： Motoharu Miyake ,  Hiroshi Inamura ,  Kazunori Yamamoto ,  Hideharu Suzuki ,  Osamu Takahashi

IPC: H04L29/02 ,  H04L1/00 ,  H04L1/18 ,  H04L12/28 ,  H04L29/06 ,  H04Q7/00

CPC classification number: H04L69/16 ,  H04L1/1825 ,  H04L1/188 ,  H04L12/5692 ,  H04L47/10 ,  H04L47/14 ,  H04L47/193 ,  H04L47/283 ,  H04L69/163 ,  H04W24/00 ,  H04W80/06

Abstract: A CPU 41 of a server device 40 measures an elapsed time after transmitting a data segment, and suspends measuring time upon receiving an acknowledgement segment for the data segment. CPU 41 transmits a data segment whose elapsed time has reached a retransmission timeout value. CPU 41 sets, as a retransmission timeout value of a data block, a time value determined according to a monotonically increasing function of a number of transmissions of the data block, during a given time period after the second-time transmission of the data block, while CPU 41 sets a time value which is predetermined and is different from the time value determined by the monotonically increasing function during a period between the first-time transmission and immediately before the second-time transmission of the data block.

Abstract translation: 服务器装置40的CPU41测量发送数据段之后的经过时间，并且在接收到数据段的确认段时暂停测量时间。 CPU41发送经过时间达到重传超时值的数据段。 作为数据块的重传超时值，CPU41在数据块的第二次发送之后的给定时间段内，设置根据数据块的传输次数的单调递增函数确定的时间值， 而CPU41在第一次发送和数据块的第二次发送之间的时段期间设置预定的时间值并且与由单调增加功能确定的时间值不同。

公开(公告)号：US20050175205A1

公开(公告)日：2005-08-11

申请号：US11053890

申请日：2005-02-10

Applicant: Osamu Takahashi

Inventor： Osamu Takahashi

IPC: H04R1/02 ,  H04R1/06 ,  H04R7/04 ,  H04R7/12 ,  H04R7/20 ,  H04R9/00 ,  H04R9/02 ,  H04R9/04 ,  H04R9/06 ,  H04R31/00

CPC classification number: H04R7/04 ,  H04R1/06 ,  H04R9/045 ,  H04R9/046 ,  H04R31/006 ,  H04R2307/207

Abstract: An oval speaker apparatus includes a diaphragm whose outer peripheral shape in a plan view is oval or elliptical; an oval or elliptical voice coil for driving the diaphragm; an edge which is joined to an outer periphery of the diaphragm; and a frame to which an outer peripheral edge of the edge is fixed. Further, lead wire which is led out from the voice coil is wired so as to traverse the surface of the edge along the minor-axis direction of the diaphragm, and is provided with slack.

Abstract translation: 椭圆形扬声器装置包括：平面图中的外周形状为椭圆形或椭圆形的隔膜; 用于驱动隔膜的椭圆形或椭圆形音圈; 连接到隔膜的外周的边缘; 以及固定边缘的外周边缘的框架。 此外，从音圈引出的引线被布线以沿着隔膜的短轴方向横越边缘的表面，并且设置有松弛。