公开(公告)号：US10304695B2

公开(公告)日：2019-05-28

申请号：US15651656

申请日：2017-07-17

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L21/00 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: An interconnect dielectric material having an opening formed therein is first provided. A surface nitridation process is then performed to form a nitridized dielectric surface layer within the interconnect dielectric material. A metal layer is formed on the nitridized dielectric surface layer and then an anneal is performed to form a metal nitride layer between the metal layer and the nitridized dielectric surface layer. A portion of the originally deposited metal layer that is not reacted with the nitridized dielectric surface is then selectively removed and thereafter an electrical conducting structure is formed directly on the metal nitride layer that is present in the opening.

公开(公告)号：US10303829B2

公开(公告)日：2019-05-28

申请号：US15609559

申请日：2017-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prasad Bhosale ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: G06F17/50 ,  H01L21/66 ,  G06N5/02

Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.

公开(公告)号：US20190148637A1

公开(公告)日：2019-05-16

申请号：US15814932

申请日：2017-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Chih-Chao Yang

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/11521 ,  H01L27/108

Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.

公开(公告)号：US20190139904A1

公开(公告)日：2019-05-09

申请号：US15806027

申请日：2017-11-07

Applicant: International Business Machines Corporation

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Griselda Bonilla

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76831 ,  H01L23/481

Abstract: An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.

公开(公告)号：US20190139821A1

公开(公告)日：2019-05-09

申请号：US15807225

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Theo Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3213

Abstract: Advanced dual damascene interconnects that exhibit controlled via resistance and, in some instances, controlled line resistance are provided. In one embodiment, the structure includes an interconnect level having a combined via/line opening located therein. A diffusion barrier liner is located in at least the via portion of the combined via/line opening. A first metallic structure composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located in at least the via portion of the combined via/line opening. A second metallic structure composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity is located in at least the line portion of the combined via/line opening. In accordance with the present application, second metallic structure is in direct contact with the first metallic structure.

公开(公告)号：US20190139820A1

公开(公告)日：2019-05-09

申请号：US15807156

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Theo Standaert

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/3213

Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.

公开(公告)号：US10283583B2

公开(公告)日：2019-05-07

申请号：US15403908

申请日：2017-01-11

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L27/08 ,  H01L23/535 ,  H01L49/02 ,  H01L21/8252 ,  H01L21/768

Abstract: The present application provides a 3D resistor structure that is embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material of the 3D resistor structure can be tuned to a desired resistivity during the manufacturing of the 3D resistor structure. Notably, a patterned doped metallic insulator is formed straddling over an dielectric pillar. A controlled surface treatment process is then performed to an upper portion of the patterned doped metallic insulator to convert the upper portion of the patterned doped metallic insulator into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining patterned doped metallic insulator and the electrical conducting resistive material.

公开(公告)号：US10256185B2

公开(公告)日：2019-04-09

申请号：US15793020

申请日：2017-10-25

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Roger A. Quon ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L23/522 ,  H01L21/3065 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.

公开(公告)号：US10217725B2

公开(公告)日：2019-02-26

申请号：US15440807

申请日：2017-02-23

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L25/065 ,  H01L21/306 ,  H01L21/324 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.

公开(公告)号：US10211148B2

公开(公告)日：2019-02-19

申请号：US14968570

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A structure comprising a first dielectric layer embedded with a first interconnect structure; an insulator layer disposed on the first dielectric layer; a second dielectric layer disposed on the insulator layer; a via residing within the second dielectric layer; and a second interconnect structure isolated from the first dielectric layer. Further, a diffusion barrier layer is configured to isolate the first interconnect structure from the first dielectric layer and the insulator layer. Further, a first portion of a bottom surface of the via resides on a top surface of the insulator layer, a second portion of the bottom surface of the via resides on a first portion of a top surface of the first interconnect structure. Moreover, a capping layer residing on a second portion of the top surface of the first interconnect structure and a first portion of a bottom surface of the second dielectric layer.