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公开(公告)号：US20230120199A1
公开(公告)日：2023-04-20
申请号：US17493884
申请日：2021-10-05
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522
摘要： A copper interconnect with an embedded dielectric cap between lines comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a first dielectric cap formed between each interconnect line of the plurality of interconnect lines. The copper interconnect further comprises a second dielectric cap formed on top of the plurality of interconnect lines and the first dielectric cap, wherein the second dielectric cap formed on top of the first dielectric cap forms a bi-layer dielectric cap between the plurality of interconnect lines.
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公开(公告)号：US20230110587A1
公开(公告)日：2023-04-13
申请号：US17450470
申请日：2021-10-11
IPC分类号： H01L23/532 , H01L23/528 , H01L23/00
摘要： A copper interconnect with self-aligned hourglass-shaped metal cap comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a metal cap formed on top of each interconnect line of the plurality of interconnect lines, where the metal cap is formed with self-aligning concave sides extending from a top surface of the dielectric layer to a top surface of the metal cap.
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公开(公告)号：US20230086420A1
公开(公告)日：2023-03-23
申请号：US17479660
申请日：2021-09-20
发明人： Hsueh-Chung Chen , Chanro Park , Koichi Motoyama , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L21/033 , H01L23/532 , H01L23/522
摘要： Methods for forming conductive lines and integrated chips include forming a mandrel on an etch stop layer. First spacers are formed on sidewalls of the mandrel. The mandrel is etched away. Conductive lines are formed on sidewalls of the first spacers. The first spacers are etched away. Dielectric spacers are formed between the conductive lines.
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公开(公告)号：US20230081953A1
公开(公告)日：2023-03-16
申请号：US17447586
申请日：2021-09-14
发明人： Saumya Sharma , Ashim Dutta , Tianji Zhou , Chih-Chao Yang
IPC分类号： H01L23/528 , H01L21/768
摘要： A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.
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公开(公告)号：US20230077760A1
公开(公告)日：2023-03-16
申请号：US17474222
申请日：2021-09-14
IPC分类号： H01L23/528 , H01L23/522 , H01L23/532 , H01L21/768
摘要： Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-κ dielectric is formed on the conformal layer such that the low-κ dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-κ dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.
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公开(公告)号：US11600325B2
公开(公告)日：2023-03-07
申请号：US17109296
申请日：2020-12-02
发明人： Hsueh-Chung Chen , Mary Claire Silvestre , Soon-Cheon Seo , Chi-Chun Liu , Fee Li Lie , Chih-Chao Yang , Yann Mignot , Theodorus E. Standaert
摘要： A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.
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公开(公告)号：US20220384564A1
公开(公告)日：2022-12-01
申请号：US17303390
申请日：2021-05-27
发明人： Hsueh-Chung Chen , Chih-Chao Yang
摘要： An interdigitated metal-insulator-metal capacitor structure is formed by a first unitary body of a first conductive material that includes a first metal plate, a first set of interdigitated electrodes protruding upwards from a top surface of the first metal plate, and a first set of connecting vias protruding downwards from a bottom surface of the first metal plate. A second unitary body of a second conductive material is disposed above the first unitary body and electrically separated from the first unitary body by an insulating layer. The second unitary body includes a second metal plate, a second set of interdigitated electrodes protruding downwards from a bottom surface of the second metal plate, and a second set of connecting vias protruding upwards from a top surface of the second metal plate. The first set of interdigitated electrodes are interleaved with the second set of interdigitated electrodes.
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公开(公告)号：US20220359814A1
公开(公告)日：2022-11-10
申请号：US17313403
申请日：2021-05-06
摘要： A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.
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公开(公告)号：US11302639B2
公开(公告)日：2022-04-12
申请号：US16744960
申请日：2020-01-16
发明人： Chih-Chao Yang , Baozhen Li , Ashim Dutta
IPC分类号： H01L23/532 , H01L23/522 , H01L43/08 , H01L27/11597 , H01L45/00 , H01L43/02 , H01L43/12 , H01L27/22 , H01L27/24
摘要： Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.
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公开(公告)号：US11289375B2
公开(公告)日：2022-03-29
申请号：US16826566
申请日：2020-03-23
IPC分类号： H01L21/768 , H01L23/522 , H01L21/02 , H01L21/311 , H01L23/532
摘要： Interconnect structures and methods for forming the interconnect structures generally include forming a dielectric layer over a substrate. The dielectric layer includes a dielectric layer top surface. A metal line is formed in the dielectric layer. The metal line includes a sacrificial upper region and a lower region. The sacrificial upper region is formed separately from the lower region and the lower region includes a lower region top surface positioned below the dielectric layer top surface. The sacrificial upper region is removed, thereby exposing the lower region top surface and forming a trench defined by the lower region top surface and sidewalls of the dielectric layer. An interconnect structure is deposited such that at least a portion of the interconnect structure fills the trench, thereby defining a fully aligned top via.
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