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111.发明授权公开(公告)号：US10203955B2
公开(公告)日：2019-02-12
申请号：US14588247
申请日：2014-12-31
申请人： Intel Corporation
发明人： Robert Valentine , Christopher J. Hughes , Mark J. Charney , Zeev Sperber , Amit Gradstein , Simon Rubanovich , Elmoustapha Ould-Ahmed-Vall , Yuri Gebil
摘要： Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.
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公开(公告)号：US20190042256A1
公开(公告)日：2019-02-07
申请号：US15858947
申请日：2017-12-29
申请人： Intel Corporation
发明人： Raanan Sade , Simon Rubanovich , Amit Gradstein , Zeev Sperber , Alexander Heinecke , Robert Valentine , Mark J. Charney , Bret Toll , Jesus Corbal , Elmoustapha Ould-Ahmed-Vall , Menachem Adelman , Eyal Hadas
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to systems and methods to zero a tile register pair. In one example, a processor includes decode circuitry to decode a matrix pair zeroing instruction having fields for an opcode and an identifier to identify a destination matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded matrix pair zeroing instruction to zero every element of a left matrix and a right matrix of the identified destination matrix.
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公开(公告)号：US20180309461A1
公开(公告)日：2018-10-25
申请号：US15922642
申请日：2018-03-15
申请人： Intel Corporation
CPC分类号： H03M7/3066 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F15/8053 , G06F15/8084
摘要： An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.
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公开(公告)号：US09946540B2
公开(公告)日：2018-04-17
申请号：US15601960
申请日：2017-05-22
申请人： Intel Corporation
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.
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公开(公告)号：US09929745B2
公开(公告)日：2018-03-27
申请号：US14499038
申请日：2014-09-26
申请人： INTEL CORPORATION
CPC分类号： H03M7/3066 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F15/8053 , G06F15/8084
摘要： An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.
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公开(公告)号：US20170123793A1
公开(公告)日：2017-05-04
申请号：US14930848
申请日：2015-11-03
申请人： Intel Corporation
发明人： Zeev Sperber , Tomer Weiner , Amit Gradstein , Simon Rubanovich , Alex Gerber , Itai Ravid
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/3832 , G06F9/384
摘要： In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.
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公开(公告)号：US09606770B2
公开(公告)日：2017-03-28
申请号：US14559160
申请日：2014-12-03
申请人： Intel Corporation
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
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公开(公告)号：US20160094241A1
公开(公告)日：2016-03-31
申请号：US14499038
申请日：2014-09-26
申请人： INTEL CORPORATION
CPC分类号： H03M7/3066 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F15/8053 , G06F15/8084
摘要： An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.
摘要翻译： 描述了用于执行向量压缩的装置和方法。 例如，处理器的一个实施例包括：矢量压缩逻辑，用于压缩包括多个有效数据元素和无效数据元素的源向量，以产生其中有效数据元素连续地存储在目的地向量的一侧上的目的地向量， 矢量压缩逻辑，以利用与源矢量相关联的位掩码，并且包括多个位，每个位对应于源向量的多个数据元素中的一个，并且指示数据元素是否包括有效数据元素或无效 数据元素，矢量压缩逻辑，以利用比特掩码的索引和比特掩码的相关比特值来生成控制向量; 并且根据控制向量来洗牌来将源向量的数据元素洗牌/排列到目的地向量。
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119.发明申请MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS 审中-公开多功能功能单元，可执行规模，圆形，GETEXP，圆形，确定，减少，范围和类别说明公开(公告)号：US20150088947A1
公开(公告)日：2015-03-26
申请号：US14559160
申请日：2014-12-03
申请人： Intel Corporation
CPC分类号： G06F7/57 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/49947 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F9/3893
摘要： A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction.
摘要翻译： 描述了涉及用功能单元执行第一指令的方法。 第一条指令是乘法加法指令。 该方法还包括执行与功能单元的第二指令。 第二个指令是一个圆形指令。
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120.发明授权公开(公告)号：US12086595B2
公开(公告)日：2024-09-10
申请号：US17214853
申请日：2021-03-27
申请人： Intel Corporation
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30025 , G06F9/30098
摘要： Systems, methods, and apparatuses relating to interleaving data values. An embodiment includes decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and execution circuitry to execute the decoded instruction according to the opcode.
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