公开(公告)号：US09292362B2

公开(公告)日：2016-03-22

申请号：US13926089

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Lev Makovsky ,  Zeev Sperber ,  Efraim Rotem ,  Nir Rosenzweig ,  Stanislav Shwartsman ,  Raanan Sade ,  Igor Yanover ,  Gavri Berger ,  Tomer Weiner ,  Ron Gabor

IPC: G06F1/04 ,  G06F9/54 ,  G06F9/30 ,  G06F9/48 ,  G06F1/32

CPC classification number: G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US11036509B2

公开(公告)日：2021-06-15

申请号：US14930848

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.

公开(公告)号：US20210357216A1

公开(公告)日：2021-11-18

申请号：US17335284

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.

公开(公告)号：US11709678B2

公开(公告)日：2023-07-25

申请号：US17335284

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/384 ,  G06F9/3861

Abstract: In one embodiment, a processor includes fetch logic to fetch instructions, decode logic to decode the fetched instructions, and execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer.

公开(公告)号：US20170123799A1

公开(公告)日：2017-05-04

申请号：US14930761

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3832 ,  G06F9/3836

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the instructions, and an execution logic to execute at least some of the instructions. The decode logic may identify a first instruction having a first immediate value, accumulate the first immediate value with a folded immediate value associated with a first operand of the first instruction, and prevent the first instruction from provision to the execution logic, such that the first instruction is not to be executed within the execution logic. Other embodiments are described and claimed.

公开(公告)号：US20230273811A1

公开(公告)日：2023-08-31

申请号：US17682091

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Eyal Oz-Sinay ,  Gavri Berger ,  Gal Ofir ,  Tomer Weiner ,  Arkady Bramnik

IPC: G06F9/48 ,  G06F9/22

CPC classification number: G06F9/4843 ,  G06F9/22

Abstract: In one embodiment, an apparatus includes: an instruction fetch circuit to fetch instructions; a decode circuit coupled to the instruction fetch circuit to decode the fetched instructions into micro-operations (pops); a scheduler coupled to the decode circuit to schedule the pops for execution; and an execution circuit coupled to the scheduler, the execution circuit comprising a plurality of execution ports to execute the pops. The scheduler may be configured to: schedule at least some pops of a first type for redundant execution on symmetric execution ports of the plurality of execution ports; and schedule pops of a second type for non-redundant execution on a single execution port of the plurality of execution ports. Other embodiments are described and claimed.

公开(公告)号：US20170123793A1

公开(公告)日：2017-05-04

申请号：US14930848

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3832 ,  G06F9/384

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.