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    INSTRUCTIONS TO CONVERT FROM FP16 TO FP8
    5.
    发明公开
    INSTRUCTIONS TO CONVERT FROM FP16 TO FP8 审中-公开

    公开(公告)号：US20240045684A1

    公开(公告)日：2024-02-08

    申请号：US17958380

    申请日：2022-10-01

    申请人： Intel Corporation

    发明人： Alexander Heinecke ,  Menachem Adelman ,  Mark Charney ,  Evangelos Georganas ,  Amit Gradstein ,  Christopher Hughes ,  Naveen Mellempudi ,  Simon Rubanovich ,  Uri Sherman ,  Zeev Sperber ,  Robert Valentine

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30036 ,  G06F9/30018

    摘要： Techniques for converting FP16 to BF8 using bias are described. An example embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed FP8 data using bias terms from the identified source/destination operand and store the packed FP8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed FP8 data using bias terms from the identified source/destination operand and store the packed FP8 data into corresponding data element positions of the identified source/destination operand.

    APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS
    6.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS 审中-公开

    公开(公告)号：US20240036865A1

    公开(公告)日：2024-02-01

    申请号：US18336985

    申请日：2023-06-17

    申请人： Intel Corporation

    发明人： Regev Shemy ,  Zeev Sperber ,  Wajdi Feghali ,  Vinodh Gopal ,  Amit Gradstein ,  Simon Rubanovich ,  Sean Gulley ,  Ilya Albrekht ,  Jacob Doweck ,  Jose Yallouz ,  Ittai Anati

    IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

    CPC分类号： G06F9/30145 ,  G06F9/30043 ,  G06F9/30196 ,  G06F9/3887 ,  H04L9/0643

    摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

    Systems and methods for performing 16-bit floating-point matrix dot product instructions
    8.
    发明授权
    Systems and methods for performing 16-bit floating-point matrix dot product instructions 有权

    公开(公告)号：US11614936B2

    公开(公告)日：2023-03-28

    申请号：US17216566

    申请日：2021-03-29

    申请人： Intel Corporation

    发明人： Alexander F. Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Raanan Sade ,  Menachem Adelman ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

    IPC分类号： G06F9/30 ,  G06F9/38

    摘要： Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

    Apparatus and method of improved insert instructions
    9.
    发明授权
    Apparatus and method of improved insert instructions 有权

    公开(公告)号：US11354124B2

    公开(公告)日：2022-06-07

    申请号：US15668508

    申请日：2017-08-03

    申请人： Intel Corporation

    发明人： Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Bret L. Toll ,  Mark J. Charney ,  Zeev Sperber ,  Amit Gradstein

    IPC分类号： G06F9/30 ,  G06F12/06 ,  G06F9/38

    摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

    APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS
    10.
    发明申请
    APPARATUSES, METHODS, AND SYSTEMS FOR HASHING INSTRUCTIONS 有权

    公开(公告)号：US20220147356A1

    公开(公告)日：2022-05-12

    申请号：US17537373

    申请日：2021-11-29

    申请人： Intel Corporation

    发明人： Regev Shemy ,  Zeev Sperber ,  Wajdi Feghali ,  Vinodh Gopal ,  Amit Gradstein ,  Simon Rubanovich ,  Sean Gulley ,  Ilya Albrekht ,  Jacob Doweck ,  Jose Yallouz ,  Ittai Anati

    IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

    摘要： Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.