公开(公告)号：US11709678B2

公开(公告)日：2023-07-25

申请号：US17335284

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/384 ,  G06F9/3861

Abstract: In one embodiment, a processor includes fetch logic to fetch instructions, decode logic to decode the fetched instructions, and execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer.

公开(公告)号：US20170123799A1

公开(公告)日：2017-05-04

申请号：US14930761

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3832 ,  G06F9/3836

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the instructions, and an execution logic to execute at least some of the instructions. The decode logic may identify a first instruction having a first immediate value, accumulate the first immediate value with a folded immediate value associated with a first operand of the first instruction, and prevent the first instruction from provision to the execution logic, such that the first instruction is not to be executed within the execution logic. Other embodiments are described and claimed.

公开(公告)号：US11036509B2

公开(公告)日：2021-06-15

申请号：US14930848

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.

公开(公告)号：US10146538B2

公开(公告)日：2018-12-04

申请号：US15282011

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Roman Dementiev ,  Ravi Rajwar ,  Ady Tal ,  Alex Gerber

IPC: G06F9/312 ,  G06F12/12 ,  G06F9/30 ,  G06F12/0855 ,  G06F12/123 ,  G06F12/0875 ,  G06F9/46 ,  G06F9/38

Abstract: Suspendable load address tracking inside transactions is disclosed. An example processing device of implementations of the disclosure includes a transactional memory (TM) read set tracking component circuitry to identify a suspend read tracking instruction within a transaction executed by the processing device, mark load instructions occurring in the transaction subsequent to the identified suspend read tracking instruction with a suspend attribute, wherein the addresses corresponding to the marked load instructions are excluded from a read set maintained for the transaction, identify a resume read tracking instruction within the transaction, and stop marking the load instructions occurring subsequent to the identified resume read tracking instruction with the suspend attribute.

公开(公告)号：US20170123793A1

公开(公告)日：2017-05-04

申请号：US14930848

申请日：2015-11-03

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/3001 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3832 ,  G06F9/384

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.

公开(公告)号：US20160026467A1

公开(公告)日：2016-01-28

申请号：US14340832

申请日：2014-07-25

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Itai Ravid ,  Gregory Pribush ,  Alex Gerber

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30192 ,  G06F9/3877

Abstract: A processor an execution unit, a decoder, an operation width tracker, and an allocator. The decoder includes logic to decode a received instruction. The operation width tracker includes logic to track a state indicating a currently used width of one or more registers of the processor. The allocator includes logic to selectively blend the instruction with a higher number of bits based upon a width of the instruction and the state. The execution unit may include logic to execute the selectively blended instructions.

Abstract translation: 处理器，执行单元，解码器，操作宽度跟踪器和分配器。 解码器包括用于解码接收到的指令的逻辑。 操作宽度跟踪器包括跟踪指示处理器的一个或多个寄存器的当前使用的宽度的状态的逻辑。 分配器包括基于指令的宽度和状态来选择性地将指令与更高位数相混合的逻辑。 执行单元可以包括执行选择性混合指令的逻辑。

公开(公告)号：US10095522B2

公开(公告)日：2018-10-09

申请号：US14581268

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/30

Abstract: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

公开(公告)号：US20180196706A1

公开(公告)日：2018-07-12

申请号：US15402835

申请日：2017-01-10

Applicant: Intel Corporation

Inventor： Alex Gerber ,  Yiannakis Sazeides ,  Arkady Bramnik ,  Ron Gabor

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/0721 ,  G06F11/0727 ,  G06F11/0751

Abstract: A processor includes physical storage locations, and a register rename unit that includes a plurality of register rename storage structures. At a given time, each of a complete group of physical storage location identifiers is to be stored in one, but only one, of the plurality of register rename storage structures, unless there is an error. Each of the complete group of physical storage location identifiers is to identify a different one of the physical storage locations. The register rename unit is to detect an error when a first value, which is to be equal to an operation on the complete group of the physical storage location identifiers with no errors, is inconsistent with a second value. The second value is to represent the operation on all physical storage location identifiers that are to be stored in the plurality of register rename storage structures at the given time.

公开(公告)号：US20170068298A1

公开(公告)日：2017-03-09

申请号：US15354018

申请日：2016-11-17

Applicant: INTEL CORPORATION

Inventor： Michael Mishaeli ,  Ron Gabor ,  Robert C. Valentine ,  Alex Gerber ,  Zeev Sperber

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3287 ,  G06F9/22 ,  Y02D10/171

Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A system on chip (SoC) includes a first functional unit, a second functional unit, and local power gate (LPG) hardware coupled to the first functional unit and the second functional unit. The LPG hardware is to power gate the first functional unit according to local power states of the LPG hardware. The second functional unit decodes a first instruction to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The second functional unit monitors a current local power state of the LPG hardware, selects a code path based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the first functional unit and continues execution of the first power-aware operation without waiting for the first functional unit to be powered up.

Abstract translation: 描述了用于功率感知操作的本地电源门（LPG）接口的技术。 片上系统（SoC）包括耦合到第一功能单元和第二功能单元的第一功能单元，第二功能单元和本地电源门（LPG）硬件。 LPG硬件根据LPG硬件的本地电源状态为第一个功能单元供电。 第二功能单元解码执行指定长度的第一功率感知操作的第一指令，包括计算用于执行的执行代码路径。 第二功能单元监视LPG硬件的当前本地电源状态，根据当前本地电源状态，指定长度和指定的阈值选择代码路径，并向LPG硬件发出提示，以启动第一个功能 并且继续执行第一功率感知操作，而不等待第一功能单元被加电。

公开(公告)号：US20210357216A1

公开(公告)日：2021-11-18

申请号：US17335284

申请日：2021-06-01

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Tomer Weiner ,  Amit Gradstein ,  Simon Rubanovich ,  Alex Gerber ,  Itai Ravid

IPC: G06F9/30

Abstract: In one embodiment, a processor includes a fetch logic to fetch instructions, a decode logic to decode the fetched instructions, and an execution logic to execute at least some of the instructions. The decode logic may determine whether a flag portion of a first instruction to be folded is to be performed, and if not, accumulate a first immediate value of the first instruction with a folded immediate value obtained from an entry of an immediate buffer. Other embodiments are described and claimed.