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    MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS
    111.
    发明申请
    MEMORY DEVICES AND METHODS WHICH MAY FACILITATE TENSOR MEMORY ACCESS 有权

    公开(公告)号：US20250147874A1

    公开(公告)日：2025-05-08

    申请号：US19016559

    申请日：2025-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

    IPC: G06F12/02 ,  G06F12/06 ,  G06F12/0864 ,  G06F12/0893

    Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

    System on a chip with deep learning accelerator and random access memory
    112.
    发明授权
    System on a chip with deep learning accelerator and random access memory 有权

    公开(公告)号：US12182704B2

    公开(公告)日：2024-12-31

    申请号：US17940343

    申请日：2022-09-08

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N5/04

    Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. An integrated circuit may be configured with: a central processing unit, a deep learning accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an artificial neural network executable by the deep learning accelerator and second instructions of an application executable by the central processing unit; one or more connections among the random access memory, the deep learning accelerator and the central processing unit; and an input/output interface to an external peripheral bus. While the deep learning accelerator is executing the first instructions to convert sensor data according to the artificial neural network to inference results, the central processing unit may execute the application that uses inference results from the artificial neural network.

    NONLINEAR DRAM DIGITAL EQUALIZATION
    113.
    发明申请
    NONLINEAR DRAM DIGITAL EQUALIZATION 有权

    公开(公告)号：US20240412050A1

    公开(公告)日：2024-12-12

    申请号：US18734380

    申请日：2024-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G06N3/048 ,  G06N3/049

    Abstract: The present disclosure relates to signal processing systems that employ various techniques to enhance data transfer quality. In some cases, a memory controller uses a neural network (e.g., time delay neural network (TDNN) to enable nonlinear processing to improve equalization. In some other cases, the memory controller uses an activation function to enable nonlinear processing to improve equalization. The systems may incorporate a finite impulse response (FIR) filter with the activation function applied to its output. A memory controller including a cache may store precomputed values of the activation function. Various types of activation functions or neural network configurations may be employed to introduce nonlinearity and adapt to different application requirements. The present disclosure is applicable in communication systems, control systems, and other digital signal processing systems requiring efficient processing of complex data transmission patterns.

    DATA CHARACTERISTIC-BASED ERROR CORRECTION SYSTEMS AND METHODS
    114.
    发明申请
    DATA CHARACTERISTIC-BASED ERROR CORRECTION SYSTEMS AND METHODS 有权

    公开(公告)号：US20240385927A1

    公开(公告)日：2024-11-21

    申请号：US18665946

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G06F11/10 ,  G06N3/06

    Abstract: Apparatuses and methods for error correction based on data characteristics are disclosed. Data characteristics can include importance of the data. Data is received at a memory controller from a host device, and a characteristic of the received data is determined. A level of error correction is selected from a plurality of error correction levels for the received data based on the determined characteristic. The received data and an error correction code are written to a memory. The error correction code is generated based on the selected level of error correction. In some implementations, the characteristic of the received data is determined using a neural network.

    Discovery of hardware characteristics of deep learning accelerators for optimization via compiler
    115.
    发明授权
    Discovery of hardware characteristics of deep learning accelerators for optimization via compiler 有权

    公开(公告)号：US12118460B2

    公开(公告)日：2024-10-15

    申请号：US17092033

    申请日：2020-11-06

    Applicant: Micron Technology, Inc.

    Inventor： Aliasger Tayeb Zaidy ,  Marko Vitez ,  Eugenio Culurciello ,  Jaime Cummins ,  Andre Xian Ming Chang

    IPC: G06N3/08 ,  G06F8/41 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06F8/41 ,  G06N3/04

    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. A computing device running a compiler can interact and/or probe an integrated circuit device to identify hardware characteristics of the integrated circuit device in performing matrix computations. The compiler can generate and optimize a result of compilation from a description of an artificial neural network based at least in part on the hardware characteristics of the integrated circuit device. The result of compilation can include first data representative of parameters of the artificial neural network and second data representative of instructions executable by the integrated circuit device to generate an output of the artificial neural network based on the first data and an input to the artificial neural network.

    INTRA-CHIP AND INTER-CHIP WIRELESS COMMUNICATIONS
    116.
    发明公开
    INTRA-CHIP AND INTER-CHIP WIRELESS COMMUNICATIONS 审中-公开

    公开(公告)号：US20240291134A1

    公开(公告)日：2024-08-29

    申请号：US18584915

    申请日：2024-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: H01Q1/22 ,  G06F13/42 ,  H04W76/16

    CPC classification number: H01Q1/2283 ,  G06F13/42 ,  H04W76/16

    Abstract: Examples described herein include an apparatus that includes a device having a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a configurable baseband processor that is configured to mix input data with a first set of weight values corresponding to a first wireless protocol to be utilized in a wireless, RF transmission to the second semiconductor chip when the input data is a first type of data and to mix the input data with a second set and to mix the input data with a second set of weight values corresponding to a second wireless protocol to be utilized in the wireless, RF transmission to the second semiconductor chip when the input data is a second type of data.

    Wireless devices and systems including examples of cross correlating wireless transmissions
    117.
    发明授权
    Wireless devices and systems including examples of cross correlating wireless transmissions 有权

    公开(公告)号：US11902411B2

    公开(公告)日：2024-02-13

    申请号：US18065097

    申请日：2022-12-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: H04L7/04 ,  H04L27/00 ,  H04L27/26

    CPC classification number: H04L7/042 ,  H04L27/0006 ,  H04L27/2647 ,  H04L27/2663 ,  H04L27/2678

    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (RF) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. The electronic device may include a comparator configured to provide a signal indicative of a presence or absence of a wireless communication signal in the particular portion of the wireless spectrum based on a comparison of the statistic with a threshold. A decoder/precoder may be configured to receive the signal indicative of the presence or absence of the wireless communication signal and to decode the symbols responsive to a signal indicative of the presence of the wireless communication signal. Examples of systems and methods described herein may facilitate the processing of data for wireless communications in a power-efficient and time-efficient manner.

    Integrated circuit device with deep learning accelerator and random access memory
    118.
    发明授权
    Integrated circuit device with deep learning accelerator and random access memory 有权

    公开(公告)号：US11874897B2

    公开(公告)日：2024-01-16

    申请号：US16844988

    申请日：2020-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Jaime Cummins

    IPC: G06F17/16 ,  G06N3/063

    CPC classification number: G06F17/16 ,  G06N3/063

    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to perform at least computations on matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; and an interface to a memory controller. The interface may be configured to facilitate access to the random access memory by the memory controller. In response to an indication provided in the random access memory, the Deep Learning Accelerator may execute the instructions to apply input that is stored in the random access memory to the Artificial Neural Network, generate output from the Artificial Neural Network, and store the output in the random access memory.

    Autocorrelation and memory allocation for wireless communication
    119.
    发明授权
    Autocorrelation and memory allocation for wireless communication 有权

    公开(公告)号：US11791872B2

    公开(公告)日：2023-10-17

    申请号：US17453914

    申请日：2021-11-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: H04B7/0456 ,  H04B7/08 ,  G06F17/15 ,  H04B7/0413 ,  H04W84/00

    CPC classification number: H04B7/0456 ,  G06F17/15 ,  G06F17/153 ,  H04B7/0413 ,  H04B7/08 ,  H04W84/005

    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first narrowband Internet of Things (IoT) transmission and a second narrowband IoT transmission. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first narrowband IoT transmission and symbols indicative of the second narrowband IoT transmission. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second narrowband IoT transmission. Examples of the systems and methods may facilitate the processing of data for wireless and may utilize less memory space than a device than a scheme that stores and calculates autocorrelation from a large dataset computed from various time points.

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