公开(公告)号：US11620088B2

公开(公告)日：2023-04-04

申请号：US17313860

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

公开(公告)号：US11604694B2

公开(公告)日：2023-03-14

申请号：US17693990

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C11/406 ,  G11C29/42 ,  G11C29/04

Abstract: Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

公开(公告)号：US20220414034A1

公开(公告)日：2022-12-29

申请号：US17929643

申请日：2022-09-02

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F1/3206 ,  G06F1/3296 ,  G06F5/06 ,  G06F1/3234

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US20220334777A1

公开(公告)日：2022-10-20

申请号：US17810527

申请日：2022-07-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US11436169B2

公开(公告)日：2022-09-06

申请号：US17207561

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G11C5/14 ,  G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US11379158B2

公开(公告)日：2022-07-05

申请号：US16820319

申请日：2020-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16

Abstract: Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory.

公开(公告)号：US11294836B2

公开(公告)日：2022-04-05

申请号：US17074281

申请日：2020-10-19

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross ,  Randall J. Rooney

IPC: G06F13/00 ,  G06F13/16 ,  G11C11/406 ,  G11C7/22 ,  G06F3/06 ,  G06F13/40

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

公开(公告)号：US11199967B2

公开(公告)日：2021-12-14

申请号：US16290126

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06

Abstract: Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state.

公开(公告)号：US20210286670A1

公开(公告)日：2021-09-16

申请号：US16816024

申请日：2020-03-11

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/408

Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

公开(公告)号：US11069394B2

公开(公告)日：2021-07-20

申请号：US16562940

申请日：2019-09-06

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Thomas H. Kinsley

IPC: G11C11/406 ,  G11C7/10 ,  G11C11/407

Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.