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    COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY
    1.
    发明公开
    COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY 审中-公开

    公开(公告)号：US20240069762A1

    公开(公告)日：2024-02-29

    申请号：US18223249

    申请日：2023-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Matthew A. Prather

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

    Abstract: An apparatus, comprising a plurality of memories and a single integrated circuit (IC) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories, and a power management integrated circuit (PMIC) module that is configured to regulate voltage and monitor current provided to the plurality of memories.

    Error check and scrub for semiconductor memory device
    4.
    发明授权
    Error check and scrub for semiconductor memory device 有权

    公开(公告)号：US11687410B2

    公开(公告)日：2023-06-27

    申请号：US17571189

    申请日：2022-01-07

    Applicant: Micron Technology, Inc.

    Inventor： Randall J. Rooney ,  Matthew A. Prather

    IPC: H03M13/09 ,  H04L1/00 ,  H04L47/125 ,  H04L45/7453 ,  G06F11/10 ,  G11C11/408 ,  G11C11/406

    CPC classification number: G06F11/1068 ,  G11C11/406 ,  G11C11/4087

    Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

    Methods for on-die memory termination and memory devices and systems employing the same
    5.
    发明授权
    Methods for on-die memory termination and memory devices and systems employing the same 有权

    公开(公告)号：US11586386B2

    公开(公告)日：2023-02-21

    申请号：US17315532

    申请日：2021-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

    IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093 ,  G06F13/40

    Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

    MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY
    6.
    发明申请
    MEMORY MAPPING FOR MEMORY, MEMORY MODULES, AND NON-VOLATILE MEMORY 有权

    公开(公告)号：US20230027332A1

    公开(公告)日：2023-01-26

    申请号：US17960523

    申请日：2022-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Frank F. Ross ,  Matthew A. Prather

    IPC: G06F9/30 ,  G06F3/06

    Abstract: Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.

    Word line characteristics monitors for memory devices and associated methods and systems
    7.
    发明授权
    Word line characteristics monitors for memory devices and associated methods and systems 有权

    公开(公告)号：US11342039B2

    公开(公告)日：2022-05-24

    申请号：US17081731

    申请日：2020-10-27

    Applicant: Micron Technology, Inc.

    Inventor： Matthew A. Prather ,  Randall J. Rooney

    IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/406 ,  G11C29/00

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

    Error correction in row hammer mitigation and target row refresh
    8.
    发明授权
    Error correction in row hammer mitigation and target row refresh 有权

    公开(公告)号：US11294762B2

    公开(公告)日：2022-04-05

    申请号：US17080238

    申请日：2020-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Randall J. Rooney ,  Matthew A. Prather

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C11/406 ,  G11C29/42 ,  G11C29/04

    Abstract: Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

    Error check and scrub for semiconductor memory device
    9.
    发明授权
    Error check and scrub for semiconductor memory device 有权

    公开(公告)号：US11221913B2

    公开(公告)日：2022-01-11

    申请号：US16816024

    申请日：2020-03-11

    Applicant: Micron Technology, Inc.

    Inventor： Randall J. Rooney ,  Matthew A. Prather

    IPC: G06F11/10 ,  G11C11/408 ,  G11C11/406

    Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

    Memory devices configured to provide external regulated voltages
    10.
    发明授权
    Memory devices configured to provide external regulated voltages 有权

    公开(公告)号：US11195569B2

    公开(公告)日：2021-12-07

    申请号：US16423427

    申请日：2019-05-28

    Applicant: Micron Technology, Inc.

    Inventor： Matthew A. Prather ,  Thomas H. Kinsley

    IPC: G11C11/4074 ,  G06F13/10 ,  G06F1/26 ,  H02M3/156

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

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