公开(公告)号：US11163490B2

公开(公告)日：2021-11-02

申请号：US16573785

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivam Swami ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  H01L27/24 ,  G06F12/02

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

公开(公告)号：US11042490B2

公开(公告)日：2021-06-22

申请号：US16192068

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

公开(公告)号：US20210089663A1

公开(公告)日：2021-03-25

申请号：US16582871

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Shivam Swami ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06F21/60 ,  G06F21/79 ,  H03K19/21

Abstract: Methods and apparatus of Exclusive OR (XOR) engine in a random access memory device to accelerate cryptographical operations in processors. For example, an integrated circuit memory device enclosed within a single integrated circuit package can include an XOR engine that is coupled with memory units in the random access memory device (e.g., having dynamic random access memory (DRAM) or non-volatile random access memory (NVRAM)). A processor (e.g., System-on-Chip (SoC) or Central Processing Unit (CPU)) can have encryption logic that performs cryptographical operations using XOR operations that are performed by the XOR engine in the random access memory device using the data in the random access memory device.

公开(公告)号：US20210081318A1

公开(公告)日：2021-03-18

申请号：US16573791

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Shivam Swami ,  Sean S. Eilert ,  Samuel E. Bradshaw

IPC: G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G11C11/00

Abstract: A system having a string of memory chips that can implement flexible provisioning of a multi-tier memory. In some examples, the system can include a first memory chip in a string of memory chips of a memory, a second memory chip in the string, and a third memory chip in the string. The first memory chip can be directly wired to the second memory chip and can be configured to interact directly with the second memory chip. The second memory chip can be directly wired to the third memory chip and can be configured to interact directly with the third memory chip. As part of implementing the flexible provisioning of a multi-tier memory, the first memory chip can include a cache for the second memory chip, and the second memory chip can include a buffer for the third memory chip.

公开(公告)号：US20210073623A1

公开(公告)日：2021-03-11

申请号：US17007588

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C11/4063

Abstract: Methods, apparatuses, and systems for in-or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US20200327942A1

公开(公告)日：2020-10-15

申请号：US16382449

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C15/04

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.