公开(公告)号：US6075409A

公开(公告)日：2000-06-13

申请号：US285116

申请日：1999-04-01

申请人： Nadim Khlat

发明人： Nadim Khlat

IPC分类号： H03D3/00 ,  H04L25/06 ,  H04L27/00

CPC分类号： H03D3/008 ,  H03D3/009 ,  H04L25/061

摘要： A method for demodulating a radio frequency signal having a frequency, by oscillating a demodulator at a frequency different from the signal frequency, and measuring a DC offset value at this different frequency, the DC offset value being associated with interference. Then the demodulator is oscillated at the signal, thereby providing a demodulated signal. The DC offset value is subtracted from the demodulated signal in order to provide a demodulated signal with a substantially reduced DC component. The demodulated signal is then monitored for further DC offset components, and these further DC offset components are subtracted from the demodulated signal.

摘要翻译： 一种用于通过以与信号频率不同的频率振荡解调器来解调具有频率的射频信号的方法，并且测量在该不同频率处的DC偏移值，该DC偏移值与干扰相关联。 然后解调器在信号处振荡，从而提供解调信号。 从解调信号中减去DC偏移值，以便提供具有基本上减小的DC分量的解调信号。 然后监视解调的信号以获得另外的DC偏移分量，并且从解调信号中减去这些另外的DC偏移分量。

公开(公告)号：US20220407465A1

公开(公告)日：2022-12-22

申请号：US17714244

申请日：2022-04-06

申请人： Nadim Khlat

发明人： Nadim Khlat

IPC分类号： H03F1/02 ,  H03F3/24

摘要： Voltage ripple suppression in a transmission circuit is disclosed. The transmission circuit includes a power amplifier circuit coupled to an envelope tracking integrated circuit (ETIC) via a conductive path. Notably, the ETIC and the conductive path can present a large source impedance to the power amplifier circuit, which can cause a ripple in the modulated voltage received by the power amplifier circuit. In a conventional approach, the large source impedance may be isolated by a large decoupling capacitor at the expense of increased voltage switching time and battery current drain. In contrast, the ETIC disclosed herein can determine and apply a correction term to the modulated voltage generated by the ETIC to thereby suppress the ripple without requiring the large decoupling capacitor. By eliminating the large decoupling capacitor, the transmission circuit can thus achieve fast voltage switching with lower battery current drain.

公开(公告)号：US09190699B2

公开(公告)日：2015-11-17

申请号：US13606139

申请日：2012-09-07

申请人： Marcus Granger-Jones ,  Nadim Khlat

发明人： Marcus Granger-Jones ,  Nadim Khlat

IPC分类号： H01P1/10 ,  H01P1/15 ,  H04B1/00 ,  H04B1/10

CPC分类号： H01P1/15 ,  H01P1/10 ,  H04B1/006 ,  H04B1/1027 ,  H04B1/109 ,  H04B2001/1054 ,  H04B2001/1063

摘要： A band switch with a switchable notch for receive carrier aggregation is disclosed. The band switch has at least one input and an output with at least one series switch coupled between the at least one input and the output. The at least one series switch is adapted to selectively couple the input to the output in response to a first control signal. The band switch also includes at least one shunt switch coupled between the at least one input and a voltage node. The at least one shunt switch is adapted to selectively couple the at least one input to the voltage node in response to a second control signal. In addition, at least one notch filter is selectively coupled to the output in a shunt configuration, wherein the at least one notch filter is configured to attenuate signals within a stop band to attenuate harmonics and distortion.

摘要翻译： 公开了具有用于接收载波聚合的可切换陷波的带开关。 带开关具有至少一个输入和输出，其中至少一个串联开关耦合在至少一个输入和输出之间。 至少一个串联开关适于响应于第一控制信号选择性地将输入耦合到输出。 带开关还包括耦合在至少一个输入端和电压节点之间的至少一个并联开关。 所述至少一个并联开关适于响应于第二控制信号选择性地将所述至少一个输入耦合到所述电压节点。 此外，至少一个陷波滤波器在分流配置中选择性地耦合到输出，其中至少一个陷波滤波器被配置为衰减阻带内的信号以衰减谐波和失真。

公开(公告)号：US08942652B2

公开(公告)日：2015-01-27

申请号：US13602856

申请日：2012-09-04

申请人： Nadim Khlat ,  Michael R. Kay ,  Philippe Gorisse

发明人： Nadim Khlat ,  Michael R. Kay ,  Philippe Gorisse

IPC分类号： H01Q11/12 ,  H04B1/04 ,  H03G1/00 ,  H03F1/02

CPC分类号： H03G1/00 ,  H03F1/0227

摘要： An envelope tracking power supply and transmitter control circuitry are disclosed. The transmitter control circuitry receives a first envelope power supply control signal and a second envelope power supply control signal. The envelope tracking power supply operates in one of a group of operating modes, which includes a first operating mode and a second operating mode. During both the first operating mode and the second operating mode, a first envelope power supply signal is provided to a driver stage based on the first envelope power supply control signal. During the first operating mode, a second envelope power supply signal is provided to a final stage based on the first envelope power supply control signal. However, during the second operating mode, the second envelope power supply signal is provided to the final stage based on the second envelope power supply control signal.

摘要翻译： 公开了一种信封跟踪电源和发射机控制电路。 发射机控制电路接收第一包络电源控制信号和第二包络电源控制信号。 信封跟踪电源以包括第一操作模式和第二操作模式的一组操作模式中的一种操作。 在第一操作模式和第二操作模式期间，基于第一包络电源控制信号将第一包络电源信号提供给驱动器级。 在第一操作模式期间，第二包络电源信号基于第一包络电源控制信号提供到最后级。 然而，在第二操作模式期间，第二包络电源信号基于第二包络电源控制信号提供到最后级。

公开(公告)号：US08787215B1

公开(公告)日：2014-07-22

申请号：US12900056

申请日：2010-10-07

申请人： Nadim Khlat ,  Marcus Granger-Jones

发明人： Nadim Khlat ,  Marcus Granger-Jones

IPC分类号： H04J3/00

CPC分类号： H04B17/102 ,  H04B1/006 ,  H04B17/318 ,  H04Q2213/13098 ,  H04W84/06

摘要： An antenna tuner unit (ATU) that includes a T/R switch integrated with a receive only tuner circuit that is made up of a relatively tiny tuner circuitry is provided. The integration of the T/R switch with the receive only tuner circuit uses a microelectronics fabrication technology like silicon-on-insulator (SOI) with minimum cascading stages. As a result, the ATU of the present invention avoids a relatively complicated and expensive technology like Micro-electromechanical systems (MEMS). The ATU of the present disclosure is applicable to fourth generation (4G) standards like long term evolution time division duplex (LTE-TDD) or for a receiver diversity system such as a multiple-input and multiple-output (MIMO) system. The control of the receive only tuner circuit is accomplished via a relatively simple one-wire general input output (GPIO) thus allowing interface with most existing or future 4G transceiver products.

摘要翻译： 提供了一种天线调谐器单元（ATU），其包括与仅由相对小的调谐器电路组成的仅接收调谐器电路集成的T / R开关。 T / R开关与仅接收调谐器电路的集成使用微电子制造技术，如具有最小级联级的绝缘体上硅（SOI）。 结果，本发明的ATU避免了相对复杂和昂贵的技术，如微机电系统（MEMS）。 本公开的ATU适用于诸如长期演进时分双工（LTE-TDD）或诸如多输入和多输出（MIMO）系统的接收机分集系统的第四代（4G）标准。 仅接收调谐器电路的控制通过相对简单的单线通用输入输出（GPIO）实现，从而允许与大多数现有或未来的4G收发器产品的接口。

公开(公告)号：US08705654B1

公开(公告)日：2014-04-22

申请号：US12901109

申请日：2010-10-08

申请人： Nadim Khlat ,  Marcus Granger-Jones ,  Alexander Wayne Hietala ,  David Cassetti

发明人： Nadim Khlat ,  Marcus Granger-Jones ,  Alexander Wayne Hietala ,  David Cassetti

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC分类号： H03F3/195 ,  H03F1/3247 ,  H03F1/3282 ,  H03F3/24 ,  H04L27/0002

摘要： The present disclosure relates to RF circuitry having delay locked loop (DLL) circuitry that may be used to measure amplitude modulation-to-phase modulation (AMPM) distortion of an RF power amplifier during factory calibration or during real time operation of the RF circuitry. During a calibration mode, the DLL circuitry may be calibrated using a reference clock signal. During a phase measurement mode, the DLL circuitry may use the reference clock signal, which is representative of an RF input signal to the RF power amplifier, and a feedback signal, which is representative of an RF output signal from the RF power amplifier, to measure a phase difference between the RF input signal and the RF output signal. By measuring the phase difference at different amplitudes of the RF output signal, the AMPM distortion of the RF power amplifier may be determined and used to correct for the AMPM distortion.

摘要翻译： 本公开涉及具有延迟锁定环（DLL）电路的RF电路，其可以用于在工厂校准期间或在RF电路的实时操作期间测量RF功率放大器的幅度调制 - 相位调制（AMPM）失真。 在校准模式期间，可以使用参考时钟信号来校准DLL电路。 在相位测量模式期间，DLL电路可以使用表示到RF功率放大器的RF输入信号的参考时钟信号，以及代表来自RF功率放大器的RF输出信号的反馈信号， 测量RF输入信号和RF输出信号之间的相位差。 通过测量RF输出信号的不同幅度的相位差，可以确定RF功率放大器的AMPM失真并用于校正AMPM失真。

公开(公告)号：US08667317B1

公开(公告)日：2014-03-04

申请号：US12884981

申请日：2010-09-17

申请人： Dharma Reddy Kadam ,  Nadim Khlat ,  Christopher Truong Ngo

发明人： Dharma Reddy Kadam ,  Nadim Khlat ,  Christopher Truong Ngo

IPC分类号： G06F1/04 ,  H04B1/38

CPC分类号： H04L7/04 ,  G06F13/385 ,  H04J3/0685

摘要： The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signal. The clock information may be associated with one or more serial communications command via the RFFE serial communications bus.

摘要翻译： 本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。 因此，RFFE电路可以使用RFFE串行通信总线彼此连接。 此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包括集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联。

公开(公告)号：US08624576B2

公开(公告)日：2014-01-07

申请号：US13222484

申请日：2011-08-31

申请人： Nadim Khlat ,  Joseph Hubert Colles

发明人： Nadim Khlat ,  Joseph Hubert Colles

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2001/009

摘要： Disclosed is a charge pump system having a charge pump with a switch control input, a voltage output terminal, a high voltage terminal coupled to a high voltage node and a low voltage terminal coupled to a low voltage node. Also included is a first buck/boost switch having a first terminal coupled to the voltage output terminal, a second terminal coupled to a first output node, and a first control terminal for receiving a first control signal. A second buck/boost switch includes a first terminal coupled to the voltage output terminal, a second terminal coupled to a second output node, and a control terminal for receiving a second control signal. Further included is a switch controller that is adapted to generate the first control signal and the second control signal such that voltage pulses output from the first output node and the second output node, respectively, are asymmetrical and coincidental.

摘要翻译： 公开了一种具有电荷泵的电荷泵系统，其具有开关控制输入端，电压输出端子，耦合到高电压节点的高电压端子和耦合到低压节点的低电压端子。 还包括第一降压/升压开关，其具有耦合到电压输出端的第一端子，耦合到第一输出节点的第二端子和用于接收第一控制信号的第一控制端子。 第二降压/升压开关包括耦合到电压输出端的第一端子，耦合到第二输出节点的第二端子和用于接收第二控制信号的控制端子。 还包括开关控制器，其适于产生第一控制信号和第二控制信号，使得分别从第一输出节点和第二输出节点输出的电压脉冲是不对称和巧合的。

公开(公告)号：US08618868B2

公开(公告)日：2013-12-31

申请号：US13222453

申请日：2011-08-31

申请人： Nadim Khlat ,  Joseph Hubert Colles

发明人： Nadim Khlat ,  Joseph Hubert Colles

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2001/009

摘要： Disclosed is a charge pump having first and second outputs and at least one capacitor. A plurality of switches are coupled to the at least one capacitor for selectively coupling the at least one capacitor between a high voltage node and a low voltage node, and for selectively coupling the at least one capacitor to the first output and the second output. A switch controller is adapted to generate control signals for the plurality of switches to selectively couple the at least one capacitor between the high voltage node and the low voltage node during charging, and to selectively couple the at least one capacitor to the first output and the second output during discharging that output a first voltage pulse from the first output and a second voltage pulse from the second output such that the first voltage pulse and the second voltage pulse are asymmetrical and coincidental.

摘要翻译： 公开了一种具有第一和第二输出的电荷泵和至少一个电容器。 多个开关耦合到所述至少一个电容器，用于选择性地将所述至少一个电容器耦合在高压节点和低电压节点之间，并且用于选择性地将所述至少一个电容器耦合到所述第一输出和所述第二输出。 开关控制器适于产生用于多个开关的控制信号，以在充电期间选择性地将高电压节点和低电压节点之间的至少一个电容器耦合，并且选择性地将至少一个电容器耦合到第一输出端 在第一输出端输出第一电压脉冲和来自第二输出的第二电压脉冲的放电期间的第二输出，使得第一电压脉冲和第二电压脉冲不对称和重合。

公开(公告)号：US08509351B1

公开(公告)日：2013-08-13

申请号：US12895223

申请日：2010-09-30

申请人： Nadim Khlat ,  Alexander Wayne Hietala ,  Marcus Granger-Jones

发明人： Nadim Khlat ,  Alexander Wayne Hietala ,  Marcus Granger-Jones

IPC分类号： H03C3/00

CPC分类号： H03C5/00 ,  H03C2200/0058

摘要： The present disclosure relates to multi-mode RF circuitry using a single IQ modulator topology that may support different communication standards, including enhanced data rates for global system for mobile communications evolution (EDGE) and EDGE evolution by dividing certain modulation functions between a frequency synthesizer and an IQ modulator. Specifically, during a standard modulation mode, which may be used to support many communications standards, the frequency synthesizer provides an un-modulated RF carrier signal to the IQ modulator, which either phase modulates or phase and amplitude modulates the un-modulated RF carrier signal to provide a standard modulated RF signal. During a small signal polar modulation mode, which may be used to support the EDGE and EDGE evolution protocols, the frequency synthesizer provides a phase-modulated RF carrier signal to the IQ modulator, which may or may not amplitude modulate the phase-modulated RF carrier signal to provide a small signal polar modulated RF signal.

摘要翻译： 本公开涉及使用可以支持不同通信标准的单个IQ调制器拓扑的多模式RF电路，包括用于移动通信演进（EDGE）的全球系统的增强的数据速率和通过在频率合成器和 一个IQ调制器。 具体地说，在可用于支持许多通信标准的标准调制模式中，频率合成器向IQ调制器提供未调制的RF载波信号，IQ调制器可以对未调制的RF载波信号进行相位调制或相位和幅度调制 以提供标准的调制RF信号。 在可以用于支持EDGE和EDGE演进协议的小信号极化调制模式中，频率合成器向IQ调制器提供相位调制的RF载波信号，IQ调制器可以或可以不对相位调制的RF载波进行幅度调制 信号提供小信号极调调制RF信号。