公开(公告)号：US5793992A

公开(公告)日：1998-08-11

申请号：US664107

申请日：1996-06-13

Applicant: James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

Inventor： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F13/362

CPC classification number: G06F13/1605 ,  G06F13/4027 ,  G06F13/4031

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.

Abstract translation: 一种计算机系统，其中主机总线从连接到输入/输出（I / O）总线（例如，外围设备）的主存储器和设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 此外，为了减少寻求通过主机总线和内部总线访问主存储器的处理器的停止，主总线能够在暂时不需要内部总线的时间期间使用内部总线来访问主存储器 通过主存储器和外围设备之间的数据传输。 因此，由于主机总线可用于其他处理操作，而不是与外围设备的数据传输相关联，因此内部总线在主存储器之间的数据传输期间偶尔被释放，因此计算机系统具有显着更好的性能 和外围设备。

公开(公告)号：US06334198B1

公开(公告)日：2001-12-25

申请号：US09283171

申请日：1999-04-01

Applicant: Swaroop Adusumilli ,  James Steele ,  David Cassetti

Inventor： Swaroop Adusumilli ,  James Steele ,  David Cassetti

IPC: G01R3128

CPC classification number: G01R31/318558 ,  G01R31/318563

Abstract: An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled at a time. For applications typically requiring that control be transferred between such TAP controllers, one embodiment of the present invention configures a TLM-based design such that multiple TAP controllers can be simultaneously enabled. This alleviates the need to actually transfer the control from one TAP controller to the next. To maintain consistency with the IEEE JTAG recommendation, the TLM-based design is configured such that only one TAP is enabled upon reset. After reset, the TLM controls the multiply-enabled TAP controllers. Another specific example implementation is directed to a circuit control arrangement for such a multi-core IC having each TAP controller generate status and test signals in response to input signals directed to each of the multiple TAP controllers. A TAP link arrangement, including a TAP link module and control signals coupled to each of the multiple TAP controllers, selectively multiplexes the input signals to the multiple TAP controllers and multiplexes the status and test signals provided by the multiple TAP controllers to an output port of the IC.

Abstract translation: 一种安排控制一个设计有多个“核心”电路（如多个CPU）的IC，每个核心电路包括其自己的TAP控制器和一次启用多个TAP控制器。 对于通常要求在这种TAP控制器之间传输控制的应用，本发明的一个实施例配置基于TLM的设计，使得可以同时启用多个TAP控制器。 这减轻了将控制从一个TAP控制器实际传输到下一个的需要。 为了保持与IEEE JTAG建议的一致性，基于TLM的设计被配置为使得在复位时仅启用一个TA​​P。 复位后，TLM控制多功能TAP控制器。 另一个具体示例实现涉及用于这种多核IC的电路控制装置，其具有每个TAP控制器响应于针对多个TAP控制器中的每一个的输入信号而产生状态和测试信号。 包括TAP链路模块和耦合到多个TAP控制器中的每一个的控制信号的TAP链路布置选择性地将输入信号复用到多个TAP控制器，并将由多个TAP控制器提供的状态和测试信号复用到 IC。

公开(公告)号：US07194766B2

公开(公告)日：2007-03-20

申请号：US09880701

申请日：2001-06-13

Applicant: Lee P. Noehring ,  Chad W. Mercer ,  David Cassetti ,  Michael Privett ,  Satish Anand

Inventor： Lee P. Noehring ,  Chad W. Mercer ,  David Cassetti ,  Michael Privett ,  Satish Anand

IPC: G06F9/00

CPC classification number: H04L63/0485 ,  H04L29/06 ,  H04L63/0236 ,  H04L63/0272 ,  H04L63/0428 ,  H04L63/08 ,  H04L63/10 ,  H04L63/164 ,  H04L63/20 ,  H04L69/04 ,  H04L69/12 ,  H04L69/22

Abstract: A packet processing system is embodied on an ASIC is optimized for processing IPSec security protocol packets in a hardware configuration. Embedded RISC processors operate with hardware support modules providing for IPSec packet processing at OC24 data rates and greater. IPSec packets are received through a streaming interface and buffered in an external memory. When the entire packet is in external memory, portions are buffered in a local memory for crypto-processing. As portions of the packets complete processing, the portions are buffered to an output portion of the external memory associated with the channel. When an entire packet competes processing, portions are buffered to a local memory for streaming. The hardware accordingly reduces the involvement of the RISC processors and significantly increases channel throughput providing for high-speed IPSec packet processing.

Abstract translation: 分组处理系统体现在ASIC上，经过优化，用于处理硬件配置中的IPSec安全协议数据包。 嵌入式RISC处理器采用硬件支持模块，以OC24数据速率和更高的速度提供IPSec数据包处理。 IPSec数据包通过流接口接收并缓存在外部存储器中。 当整个数据包在外部存储器中时，部分缓冲在本地存储器中用于加密处理。 随着分组的一部分完成处理，这些部分被缓冲到与该信道相关联的外部存储器的输出部分。 当整个分组竞争处理时，部分被缓冲到本地存储器以进行流传输。 因此硬件相应地减少了RISC处理器的参与，并显着增加了提供高速IPSec数据包处理的信道吞吐量。

公开(公告)号：US06311302B1

公开(公告)日：2001-10-30

申请号：US09283648

申请日：1999-04-01

Applicant: David Cassetti ,  James Steele ,  Swaroop Adusumilli

Inventor： David Cassetti ,  James Steele ,  Swaroop Adusumilli

IPC: G01R3128

CPC classification number: G01R31/318536

Abstract: An arrangement controls an IC designed with multiple “TLM'ed core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple “TLM'ed core” circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

Abstract translation: 一种安排控制一个设计有多个“TLM”核心“电路的IC，如多个CPU，每个核心电路包括其自己的TAP控制器，并且启用了多个TAP控制器。 对于通常需要在各种核心电路的这种TAP控制器之间传输控制的应用，本发明的一个实施例扩展了多个“TLM”核心“电路设计而不改变IEEE JTAG规范，并且不需要每个TAP的更多的扫描链 核心。 一个具体示例性实施例包括设计的多个核心中的每一个，包括多个测试访问端口（TAP）控制器，并且包括具有适于存储可解码指令的TLM寄存器的内部TLM和适于存储编码信号的补充存储电路。 同样在设计中，芯片级TLM通过TLM寄存器和补充存储电路与普通的IEEE JTAG接口和多个内核中的每一个进行通信。 芯片级TLM和多核心信号使用补充存储电路来指示何时将指令从TLM的内核传送到芯片级的TLM。

公开(公告)号：US08705654B1

公开(公告)日：2014-04-22

申请号：US12901109

申请日：2010-10-08

Applicant: Nadim Khlat ,  Marcus Granger-Jones ,  Alexander Wayne Hietala ,  David Cassetti

Inventor： Nadim Khlat ,  Marcus Granger-Jones ,  Alexander Wayne Hietala ,  David Cassetti

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC classification number: H03F3/195 ,  H03F1/3247 ,  H03F1/3282 ,  H03F3/24 ,  H04L27/0002

Abstract: The present disclosure relates to RF circuitry having delay locked loop (DLL) circuitry that may be used to measure amplitude modulation-to-phase modulation (AMPM) distortion of an RF power amplifier during factory calibration or during real time operation of the RF circuitry. During a calibration mode, the DLL circuitry may be calibrated using a reference clock signal. During a phase measurement mode, the DLL circuitry may use the reference clock signal, which is representative of an RF input signal to the RF power amplifier, and a feedback signal, which is representative of an RF output signal from the RF power amplifier, to measure a phase difference between the RF input signal and the RF output signal. By measuring the phase difference at different amplitudes of the RF output signal, the AMPM distortion of the RF power amplifier may be determined and used to correct for the AMPM distortion.

Abstract translation: 本公开涉及具有延迟锁定环（DLL）电路的RF电路，其可以用于在工厂校准期间或在RF电路的实时操作期间测量RF功率放大器的幅度调制 - 相位调制（AMPM）失真。 在校准模式期间，可以使用参考时钟信号来校准DLL电路。 在相位测量模式期间，DLL电路可以使用表示到RF功率放大器的RF输入信号的参考时钟信号，以及代表来自RF功率放大器的RF输出信号的反馈信号， 测量RF输入信号和RF输出信号之间的相位差。 通过测量RF输出信号的不同幅度的相位差，可以确定RF功率放大器的AMPM失真并用于校正AMPM失真。

公开(公告)号：US06385749B1

公开(公告)日：2002-05-07

申请号：US09283809

申请日：1999-04-01

Applicant: Swaroop Adusumilli ,  James Steele ,  David Cassetti

Inventor： Swaroop Adusumilli ,  James Steele ,  David Cassetti

IPC: G01R3128

CPC classification number: G01R31/318563 ,  G01R31/318555

Abstract: An arrangement controls an IC designed with multiple “core” circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

Abstract translation: 一种布置控制了设计有多个“核心”电路的IC，例如多个CPU，每个核心电路包括其自己的TAP控制器。 根据一个示例性实施例，耦合到公共接口的多个测试访问端口（TAP）控制器通过使每个TAP控制器适配以接收输入信号，确定TAP控制器是否被使能并产生状态信号和测试信号来控制。 输出电路通过输出由多个TAP控制器分别提供的一个测试信号来响应于TAP控制器，并且链路模块用于在给定时间内维持其中一个TAP控制器的使能。 上述实施例例如与需要越来越多的核心电路的IC应用有关，而不增加IC的电路面积和/或IC引脚的数量，并且可以实现以避免改变现有的结构 TAP控制器。

公开(公告)号：US5815675A

公开(公告)日：1998-09-29

申请号：US670273

申请日：1996-06-13

Applicant: James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

Inventor： James C. Steele ,  Barry Davis ,  Philip Wszolek ,  Brian Fall ,  Swaroop Adusumilli ,  David Cassetti ,  Rodney Pesavento ,  Nick Richardson

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F13/161 ,  G06F12/0835

Abstract: A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e.g., peripheral devices) connected to the I/O bus.

Abstract translation: 一种计算机系统，其中主机总线从主存储器和连接到输入/输出（I / O）总线的设备之间的数据传输负担中减轻。 相反，本发明操作来将数据传输的大部分负担置于总线仲裁单元内的内部总线上，使得主机总线比传统实现更早地释放。 因此，由于主机总线可用于其他处理操作，而不是与连接到I / O总线的设备（例如，外围设备）进行数据传输相结合，因此计算机系统具有显着更好的性能。