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公开(公告)号：US20230388536A1
公开(公告)日：2023-11-30
申请号：US18226952
申请日：2023-07-27
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/52 , H04N19/137 , H04N19/186
CPC classification number: H04N19/52 , H04N19/137 , H04N19/186 , H04N19/176
Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.
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公开(公告)号：US20230362397A1
公开(公告)日：2023-11-09
申请号：US18355164
申请日：2023-07-19
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/44 , H04N19/105 , H04N19/139 , H04N19/176 , H04N19/513
CPC classification number: H04N19/44 , H04N19/105 , H04N19/139 , H04N19/176 , H04N19/521
Abstract: An image encoder includes circuitry and a memory, wherein the circuitry, in operation, determines whether inter prediction is to be applied to a current block; in response to determining that the inter prediction is to be applied to the current block, performs a partition prediction process; and, in response to determining that the inter prediction is not to be applied, encodes the current block without using the partition prediction process. The partition prediction process includes predicting first values of a set of pixels between a first partition and a second partition in the current block, using a first motion vector for the first partition; predicting second values of the set of pixels, using a second motion vector for the second partition; weighting the first values and the second values; and generating a prediction image for the current block using the weighted first values and the weighted second values.
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公开(公告)号：US20230308692A1
公开(公告)日：2023-09-28
申请号：US18325906
申请日：2023-05-30
Inventor： Ryuichi KANOH , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/96 , H04N19/124 , H04N19/159 , H04N19/176 , H04N19/18 , H04N19/66 , H04N19/91
CPC classification number: H04N19/96 , H04N19/124 , H04N19/159 , H04N19/176 , H04N19/18 , H04N19/66 , H04N19/91
Abstract: An image encoder performs a first partitioning including using a first partition mode, without writing first splitting information indicative of the first partition mode into a bitstream, to split a first block into a plurality of second blocks in response to that the first block is located adjacent to an edge of a picture and that the dimensions of the first block satisfy a first condition; and performs a second partitioning on the second block by writing second splitting information indicative of a second partition mode into the bitstream, wherein the second partition mode allows at least one of a quad tree splitting and a binary splitting, and using the second partition mode to split the second block into a plurality of coding units (CUs), wherein the second partition mode prohibits the quad tree splitting of the second block in certain conditions.
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公开(公告)号：US20230276068A1
公开(公告)日：2023-08-31
申请号：US18142173
申请日：2023-05-02
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Takashi HASHIMOTO
IPC: H04N19/52 , H04N19/124 , H04N19/159 , H04N19/176
CPC classification number: H04N19/52 , H04N19/124 , H04N19/159 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.
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公开(公告)号：US20230262231A1
公开(公告)日：2023-08-17
申请号：US18135997
申请日：2023-04-18
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH
IPC: H04N19/159 , H04N19/105 , H04N19/176 , H04N19/186 , H04N19/583
CPC classification number: H04N19/159 , H04N19/105 , H04N19/176 , H04N19/186 , H04N19/583
Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.
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Patent Agency Ranking
116.发明公开公开(公告)号：US20230171423A1
公开(公告)日：2023-06-01
申请号：US18103567
申请日：2023-01-31
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/513 , H04N19/132 , H04N19/176 , H04N19/563
CPC classification number: H04N19/513 , H04N19/132 , H04N19/176 , H04N19/563
Abstract: The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.
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117.发明公开公开(公告)号：US20230156214A1
公开(公告)日：2023-05-18
申请号：US18067519
申请日：2022-12-16
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/51 , H04N19/176 , H04N19/182
CPC classification number: H04N19/51 , H04N19/176 , H04N19/182
Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
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公开(公告)号：US20230083364A1
公开(公告)日：2023-03-16
申请号：US18056542
申请日：2022-11-17
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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公开(公告)号：US20230075757A1
公开(公告)日：2023-03-09
申请号：US18056136
申请日：2022-11-16
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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公开(公告)号：US20230074948A1
公开(公告)日：2023-03-09
申请号：US17984675
申请日：2022-11-10
Inventor： Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: encodes one or more pictures which have common time information and each of which is included in a different layer; adds the one or more pictures into one access unit in a bitstream; and adds, into the bitstream, a first flag indicating that a total number of access units present in the bitstream is one.
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