SYNCHRONOUS RECTIFICATION CIRCUIT HAVING BURST MODE CONTROLLER AND CONTROLLING METHOD THEREOF
    122.
    发明申请
    SYNCHRONOUS RECTIFICATION CIRCUIT HAVING BURST MODE CONTROLLER AND CONTROLLING METHOD THEREOF 有权
    具有脉冲模式控制器的同步整流电路及其控制方法

    公开(公告)号:US20090244934A1

    公开(公告)日:2009-10-01

    申请号:US12412979

    申请日:2009-03-27

    CPC classification number: H02M3/33592 H02M3/3378 Y02B70/1433 Y02B70/1475

    Abstract: The configuration of a synchronous rectification circuit and a controlling method thereof are provided. The proposed circuit includes a converter including a first switch and a first synchronous rectifier, and a burst mode controller including a logic process module performing one of functions of delaying one of a non-integer and at least one operating periods to generate a synchronous rectification driving signal of the first synchronous rectifier counting from a beginning of a first pulse of a driving signal of the first switch during a working time of a burst period, and turning off the synchronous rectification driving signal of the first synchronous rectifier by one of the non-integer operating period and the at least one operating period ahead of an ending of a last operating period of the driving signal of the first switch during the working time of the burst period.

    Abstract translation: 提供同步整流电路的结构及其控制方法。 所提出的电路包括包括第一开关和第一同步整流器的转换器,以及突发模式控制器,其包括执行延迟非整数和至少一个操作周期之一的功能之一的逻辑处理模块,以产生同步整流驱动 所述第一同步整流器在突发周期的工作时间期间从所述第一开关的驱动信号的第一脉冲的开始开始计数所述第一同步整流器的信号,并且通过所述非易失性存储器中的一个关闭所述第一同步整流器的同步整流驱动信号, 整数运行周期和在突发周期的工作时间期间第一开关的驱动信号的最后操作周期的结束之前的至少一个操作周期。

    SYSTEM AND METHOD FOR DETERMINING CIRCUIT FUNCTIONALITY UNDER VARYING EXTERNAL OPERATING CONDITIONS
    124.
    发明申请
    SYSTEM AND METHOD FOR DETERMINING CIRCUIT FUNCTIONALITY UNDER VARYING EXTERNAL OPERATING CONDITIONS 审中-公开
    用于确定外部操作条件变化的电路功能的系统和方法

    公开(公告)号:US20090219032A1

    公开(公告)日:2009-09-03

    申请号:US12039333

    申请日:2008-02-28

    CPC classification number: G01R31/3004 G01R31/31711

    Abstract: A system and method for determining circuit functionality under varying external operating conditions. One embodiment provides a circuit for a given input signal. Internal signals are generated at internal nodes for the given input signal and the next set of external operating conditions. The internal signals are compared with internal reference signals to determine whether the integrated circuit is functional under the next set of external operating conditions. If the circuit is found functional under the next set of external operating conditions, then the internal reference signals are set equal to the internal signals, the initial set of external operating conditions are set equal to the next set of external operating conditions, and the above described method is repeated.

    Abstract translation: 用于在变化的外部操作条件下确定电路功能的系统和方法。 一个实施例提供了用于给定输入信号的电路。 在给定输入信号和下一组外部操作条件的内部节点处产生内部信号。 将内部信号与内部参考信号进行比较,以确定集成电路在下一组外部操作条件下是否工作。 如果在下一组外部工作条件下电路被找到功能,则将内部参考信号设置为等于内部信号,将外部操作条件的初始设置设置为等于下一组外部操作条件,并且上述 重复上述方法。

    SEPARATION AND EXTRACTION SYSTEM
    128.
    发明申请
    SEPARATION AND EXTRACTION SYSTEM 审中-公开
    分离和萃取系统

    公开(公告)号:US20090090894A1

    公开(公告)日:2009-04-09

    申请号:US11868355

    申请日:2007-10-05

    CPC classification number: B01D11/0492 C07C253/34 C07C255/03

    Abstract: Extraction systems comprising acetonitrile, water, and a saccharide selected from the group consisting of a monosaccharide, an oligosaccharide, and mixtures thereof. The systems comprise a first phase and a second phase, and the concentration of the saccharide is at least 0.5 weight/volume %.

    Abstract translation: 包含乙腈,水和选自单糖,低聚糖及其混合物的糖类的提取系统。 该系统包括第一相和第二相,糖的浓度为至少0.5重量/体积%。

    High voltage FET gate structure
    130.
    发明授权
    High voltage FET gate structure 有权
    高压FET栅极结构

    公开(公告)号:US07375398B2

    公开(公告)日:2008-05-20

    申请号:US11138888

    申请日:2005-05-26

    Abstract: A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.

    Abstract translation: 用于在高电压下操作的FET器件包括分别掺杂有第一类型和第二类型的植入物的衬底,衬底内的第一阱和第二阱。 第一和第二阱限定p-n结。 第二阱内的场氧化物层限定了接收漏极接触的第一表面区域。 第三阱至少部分地位于第一阱中,包括第二类型的掺杂植入物,并且适于接收源极接触。 这样,第三井在第一井内定义了自身与第二井之间的通道。 通道上设置一个门。 栅极的至少第一部分设置在p-n结上方,并且包括第一类型的掺杂植入物。 许多排列允许掺杂栅极的其余部分。

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