公开(公告)号：US20230185483A1

公开(公告)日：2023-06-15

申请号：US17550914

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Joseph Harold Steinmetz ,  Luca Bert

IPC: G06F3/06 ,  G06F7/544

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0625 ,  G06F3/0679 ,  G06F7/5443

Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The SSD has a computation accelerator adapted to accelerate computations involved in generation of proof of space plots, such as computations of Basic Linear Algebra Subprograms (BLAS), multiplication and accumulation operations, and cryptographic operations.

公开(公告)号：US20230185476A1

公开(公告)日：2023-06-15

申请号：US17550967

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph Harold Steinmetz

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0631 ,  G06F3/0604 ,  G06F3/0679

Abstract: An apparatus with a solid state drive (SSD) having firmware to manage spare storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. The firmware is executable in the SSD to allocate storage resources not used or allocated by the host system to support proof of space activities and dynamically return the allocated storage resources when execution of a command from the host system needs additional storage resources.

公开(公告)号：US11593133B2

公开(公告)日：2023-02-28

申请号：US17742299

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F9/455 ,  G06F3/06 ,  G06F12/02 ,  G06F13/38

Abstract: A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.

公开(公告)号：US20220350759A1

公开(公告)日：2022-11-03

申请号：US17866717

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Joseph H. Steinmetz ,  Luca Bert ,  William Akin

IPC: G06F13/16 ,  G06F11/07 ,  G06F13/42

Abstract: A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

公开(公告)号：US20220334740A1

公开(公告)日：2022-10-20

申请号：US17232971

申请日：2021-04-16

Applicant: Micron Technology, Inc.

Inventor： Joseph H. Steinmetz ,  Luca Bert ,  William Akin

IPC: G06F3/06 ,  G06F12/0808

Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

公开(公告)号：US20220308780A1

公开(公告)日：2022-09-29

申请号：US17301213

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Kumar VKH Kanteti ,  Luca Bert

IPC: G06F3/06

Abstract: A memory sub-system can determine a block granularity for an input/output (I/O) data stream received from a host system. The memory sub-system can determine that the block granularity is different than a memory block granularity of a first memory region in a first namespace of the one or more memory devices, where the first memory region is to store the I/O data stream. The memory sub-system can accumulate blocks from the I/O data stream in a second memory region in a second namespace of the one or more memory devices. Responsive to a capacity of the accumulated blocks in the second memory region satisfying a threshold criterion, the memory sub-system can migrate the accumulated plurality of blocks from the second memory region to the first memory region.

公开(公告)号：US20220300376A1

公开(公告)日：2022-09-22

申请号：US17207424

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F11/14 ,  G06F3/06

Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of at least one memory device of the set, wherein the failure affects stored data; notifying a host system of a change in a capacity of the set of memory devices; receiving from the host system an indication to continue at a reduced capacity; and updating the set of memory devices to change the capacity to the reduced capacity.

公开(公告)号：US20220300195A1

公开(公告)日：2022-09-22

申请号：US17208653

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06

Abstract: Host data associated with a first region of a memory device is identified. The host data is stored in a buffer, and the first region of the memory device is designated as open. The host data is padded to a predetermined size and written to the first region of the memory device. A context associated with the first region of the memory device is updated. The first region of the memory device is designated as closed.

公开(公告)号：US20220197556A1

公开(公告)日：2022-06-23

申请号：US17147834

申请日：2021-01-13

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Joseph H. Steinmetz

IPC: G06F3/06

Abstract: A host command is received to configure a system to have a configuration designating a first interface standard at a first port for exposing a storage element and a second interface standard at a second port for exposing a persistent memory region (PMR). The storage element is implemented on a first memory device of the system and the PMR is implemented on a second memory device of the system. The second interface standard implements one or more alternate protocols supported by the first interface standard. The system is configured in accordance with the configuration.

公开(公告)号：US20220188231A1

公开(公告)日：2022-06-16

申请号：US17688506

申请日：2022-03-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca Bert

IPC: G06F12/0808 ,  G06F12/0871

Abstract: A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.