公开(公告)号：US20230074281A1

公开(公告)日：2023-03-09

申请号：US17987633

申请日：2022-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH ,  Chong Soon LIM ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/176

Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.

公开(公告)号：US20220385908A1

公开(公告)日：2022-12-01

申请号：US17883445

申请日：2022-08-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/126 ,  H04N19/30 ,  H04N19/18 ,  H04N19/176

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US20220385899A1

公开(公告)日：2022-12-01

申请号：US17868199

申请日：2022-07-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Han Boon TEO ,  Hai Wei SUN ,  Chong Soon LIM ,  Jing Ya LI ,  Chu Tong WANG ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/117 ,  H04N19/80 ,  H04N19/105 ,  H04N19/46

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry: executes a second process of applying a second filter to the first image to generate a second image, not holding the second image as a reference image, holding the first image as a reference image, and displaying the second image; writes coefficients of each of one or more filter candidates that are candidates for the second filter into a bitstream, wherein the coefficients are included in a first storage location when written into the bitstream; and writes a parameter that specifies, for each image, one of the one or more filter candidates as the second filter into the bitstream, wherein the parameter is included in a second storage location when written into the bitstream, and the second storage location is different from the first storage location.

公开(公告)号：US20220368950A1

公开(公告)日：2022-11-17

申请号：US17873754

申请日：2022-07-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato OHKAWA ,  Hideo SAITOU ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/80 ,  H04N19/176 ,  H04N19/86

Abstract: For a location displaced by four samples in a vertical direction or a horizontal direction from a current location, the encoder performs a first determination of determining only whether the location displaced by four samples is a TU boundary, where the current location is a sample location of a current sub-block boundary on which the determination process is to be performed. In the first determination, when it is determined that the location displaced by four samples is a TU boundary, the encoder sets a maximum filter length to a first value, and in the case otherwise, the encoder performs a second determination of determining whether a location displaced by eight samples in the vertical direction or the horizontal direction from the current location is a TU boundary.

公开(公告)号：US20220360811A1

公开(公告)日：2022-11-10

申请号：US17864906

申请日：2022-07-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Ru Ling LIAO ,  Han Boon TEO ,  Hai Wei SUN ,  Che Wei KUO ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/513 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176

Abstract: Provided is an encoder including circuitry and memory coupled to the circuitry. A prediction mode for a current block is an affine mode, and in operation, the circuitry: derives a base motion vector which is a motion vector to be used in a prediction process for the current block, and is a motion vector at an affine-mode control point in the current block; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; if so, modifies a second motion vector different from the base motion vector and the first motion vector, and if not, does not modify the second motion vector; and encodes the current block using the second motion vector modified or the second motion vector not modified.

公开(公告)号：US20220329785A1

公开(公告)日：2022-10-13

申请号：US17844936

申请日：2022-06-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/105 ,  H04N19/15

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry switches between storing and not storing of a decoded picture buffer (DPB) parameter related to a DPB in a common header shared between layers in layer groups each including at least one output layer, according to whether or not all the layer groups in a bitstream each include only one layer.

公开(公告)号：US20220321920A1

公开(公告)日：2022-10-06

申请号：US17832973

申请日：2022-06-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/70 ,  H04N19/186 ,  H04N19/132 ,  H04N19/167

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry determines whether or not a current video to be processed is a progressive video. When it is determined that the current video is a progressive video, the encoder encodes, into a bitstream, one syntax element indicating a chroma location type which is information indicating locations of chroma samples relative to luma samples for a frame included in the current video. When it is determined that the current video is not a progressive video, the encoder encodes two syntax elements into the bitstream, each of which indicates the chroma location type for a different one of fields of two types included in the current video.

公开(公告)号：US20220295113A1

公开(公告)日：2022-09-15

申请号：US17830577

申请日：2022-06-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Takahiro NISHI ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/70 ,  H04N19/174 ,  H04N19/172

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry: assigns a picture level slice index and a subpicture level slice index to each of the slices, the picture level slice index being assigned at a picture level, the subpicture level slice index being assigned at a subpicture level; for each of the slices, encodes the subpicture level slice index of the slice into a slice header of the slice; and encodes each of the slices into a bitstream. The picture level slice index assigned to a current slice to be processed that is included in a current subpicture to be processed is calculated by adding (i) the subpicture level slice index of the current slice and (ii) a total number of slices included in one or more subpictures that have been encoded prior to the current subpicture out of the subpictures.

公开(公告)号：US20220279180A1

公开(公告)日：2022-09-01

申请号：US17725113

申请日：2022-04-20

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/176

Abstract: Provided is an encoder which includes circuitry and memory. The circuitry encodes an image block using the memory. In encoding the image block, the circuitry: obtains one or more size parameters related to a size of the image block; determines whether the one or more size parameters and one or more thresholds satisfy a determined relationship; encodes a split parameter when the one or more size parameters and the one or more thresholds are determined to satisfy the determined relationship, the split parameter indicating whether the image block is to be split into a plurality of partitions including a non-rectangular partition; and encodes the image block after splitting the image block into the plurality of partitions when the split parameter indicates that the image block is to be split into the plurality of partitions.

公开(公告)号：US20220264090A1

公开(公告)日：2022-08-18

申请号：US17735938

申请日：2022-05-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

Abstract: An encoding method includes: changing values of luma pixels in a first block and a second block to filter a first boundary between the first block and the second block, using clipping such that change amounts of the respective values are within respective luma clip widths, the luma pixels in the first block and the second block being arranged along a first line across the first boundary; and changing values of chroma pixels in a third block and a fourth block to filter a second boundary between the third block and the fourth block, using clipping such that change amounts of the respective values are within respective chroma clip widths, the chroma pixels in the third block and the fourth block being arranged along a second line across the second boundary. The luma clip widths applied to the luma pixels are selected to be asymmetrical relative to the first boundary.