公开(公告)号：US06191976B1

公开(公告)日：2001-02-20

申请号：US09372730

申请日：1999-08-11

申请人： Michael C. Smayling ,  Giulio G. Marotta ,  Giovanni Santin

发明人： Michael C. Smayling ,  Giulio G. Marotta ,  Giovanni Santin

IPC分类号： G11C1606

CPC分类号： G11C16/28 ,  G11C16/3436

摘要： FLASH Memory sense amplifier reference circuit with weighted dummy loads is used to balance and bias the sense amplifier during erasing, programming, and verification such that the resulting robust stored logic states can meet more stringent pass-fail verify “1” or verify “0” tests. Programming in this manner guarantees logic states which meet full operating temperature and full power supply tolerances requirements.

摘要翻译： 闪存具有加权虚拟负载的存储器读出放大器参考电路用于在擦除，编程和验证期间平衡和偏置读出放大器，使得得到的鲁棒存储逻辑状态可以满足更严格的通过失败验证“1”或验证“0” 测试。 以这种方式进行编程可确保满足全部工作温度和全部电源容限要求的逻辑状态。

公开(公告)号：US5504708A

公开(公告)日：1996-04-02

申请号：US369025

申请日：1995-01-05

申请人： Giovanni Santin ,  Giovanni Naso ,  Sebastiano D'Arrigo ,  Michael C. Smayling

发明人： Giovanni Santin ,  Giovanni Naso ,  Sebastiano D'Arrigo ,  Michael C. Smayling

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

公开(公告)号：US08045386B2

公开(公告)日：2011-10-25

申请号：US12820430

申请日：2010-06-22

申请人： Giovanni Santin ,  Michele Incarnati

发明人： Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected memory cell of a string of memory cells, and applying a cutoff voltage to a set of one or more memory cells of the string between the selected memory cell and a select gate. The methods further include applying a pass voltage to one or more other memory cells of the string between the selected memory cell and the select gate. Other methods further include applying other pass voltages, other cutoff voltages and/or intermediate voltages to still other memory cells of the string.

摘要翻译： 使用一个或多个阻塞存储器单元来编程存储器单元的方法和装置有助于缓解电容性电压耦合。 所述方法包括将程序电压施加到存储器单元串的所选择的存储单元，以及将所述截止电压施加到所选存储单元和选择栅极之间的所述串的一个或多个存储单元的集合。 所述方法还包括将通过电压施加到所选择的存储器单元和选择栅极之间的串的一个或多个其它存储单元。 其他方法还包括将其他通过电压，其它截止电压和/或中间电压应用于串的其他存储单元。

公开(公告)号：US07911865B2

公开(公告)日：2011-03-22

申请号：US12613114

申请日：2009-11-05

申请人： Michele Incarnati ,  Giovanni Santin

发明人： Michele Incarnati ,  Giovanni Santin

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C5/143

摘要： A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.

摘要翻译： 温度传感器产生集成电路的温度的数字表示。 逻辑电路读取数字温度并产生作为集成电路温度的函数的定时信号的工作电压和多位数字表示的多位数字表示。 电压发生器将操作电压的数字表示转换为模拟电压，该模拟电压偏置需要温度补偿电压的集成电路的部分。 在一个实施例中，温度补偿电压偏置存储器单元。 定时发生器将定时信号的多位数字表示转换为逻辑信号。

公开(公告)号：US07742338B2

公开(公告)日：2010-06-22

申请号：US11973733

申请日：2007-10-10

申请人： Giovanni Santin ,  Michele Incarnati

发明人： Giovanni Santin ,  Michele Incarnati

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by utilizing sets of two or more adjacent word lines and applying the same voltage to each in array access operations. This allows each word line of the set or pair to shield the other from word line to word line capacitive voltage coupling. In NAND memory string embodiments the various cells of strings of non-volatile memory cells are programmed utilizing modified or unmodified drain-side self boost, source-side self boost, local self boost, and virtual ground programming processes that utilize two or more “blocking” memory cells on either the source line side and drain line side of a selected memory cell. The paired blocking cells shield each other during programming to reduce coupled noise, to prevent charge leakage from the boosted channel of the selected memory cell.

摘要翻译： 描述了NAND​​架构非易失性存储器件和编程过程，其通过利用两个或更多个相邻字线的集合并将阵列访问操作中的每一个施加相同的电压来减少字线对字线电压耦合的影响。 这允许集合或对的每个字线将另一个字符从字线屏蔽到字线电容电压耦合。 在NAND存储器串实施例中，使用经修改或未修改的漏极侧自增强，源侧自增强，局部自增强和使用两个或多个“阻塞”的虚拟地面编程过程来编程非易失性存储器单元串的各个单元 “存储单元位于所选存储单元的源极线侧和漏极线侧上。 配对的阻塞单元在编程期间相互屏蔽以减少耦合噪声，以防止来自所选存储单元的升压通道的电荷泄漏。

公开(公告)号：US07280420B2

公开(公告)日：2007-10-09

申请号：US11430549

申请日：2006-05-09

申请人： Giovanni Santin

发明人： Giovanni Santin

IPC分类号： G11C7/00

CPC分类号： G11C29/1201 ,  G11C29/40

摘要： Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

摘要翻译： 具有正常操作模式和测试操作模式的存储器件在质量程序中是有用的。 测试操作模式包括数据压缩测试模式。 在数据压缩测试模式中，读取输出页面的一个字提供输出页面的剩余字的数据值的指示。 读取和验证重复测试模式所需的时间可以减少，因为只需要读取每个输出页面的一个单词，以确定存储器件准确地写入和存储数据值的能力。 存储器件包括数据压缩电路，用于比较输出页面每个字的每个比特位置的数据值。 如果输出页面的一个字的位位置与数据值不同于输出页面的任何剩余字，则选择性地禁用输出。

公开(公告)号：US07209403B2

公开(公告)日：2007-04-24

申请号：US10716766

申请日：2003-11-19

申请人： Giovanni Santin

发明人： Giovanni Santin

IPC分类号： G11C17/18

CPC分类号： G11C29/70

摘要： An enhanced fuse circuit is discussed that advances redundancy techniques in integrated circuits. The enhanced fuse circuit uses a single nonvolatile fuse and a latch that is coupled at a desired time. One embodiment of the invention discusses a fuse circuit that includes a volatile latch and a nonvolatile fuse. The nonvolatile fuse adapts to operate with a voltage supply greater than about 1.65 volts. The voltage supply is boosted at a desired time to a predetermined level and for a predetermined duration so that the nonvolatile fuse transfers its data to the volatile latch.

摘要翻译： 讨论了一种增强型熔丝电路，用于提高集成电路中的冗余技术。 增强熔丝电路使用单个非易失性熔丝和在期望时间耦合的锁存器。 本发明的一个实施例讨论了包括易失性锁存器和非易失性熔断器的熔丝电路。 非易失性熔断器适用于大于1.65伏特的电源。 电压源在期望的时间被提升到预定电平并达预定的持续时间，使得非易失性熔丝将其数据传送到易失性锁存器。

公开(公告)号：US20060221737A1

公开(公告)日：2006-10-05

申请号：US11430549

申请日：2006-05-09

申请人： Giovanni Santin

发明人： Giovanni Santin

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/1201 ,  G11C29/40

摘要： Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

公开(公告)号：US20060215470A1

公开(公告)日：2006-09-28

申请号：US11430550

申请日：2006-05-09

申请人： Giovanni Santin

发明人： Giovanni Santin

IPC分类号： G11C29/00

CPC分类号： G11C29/1201 ,  G11C29/40

摘要： Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode. In the data compression test mode, reading one word of an output page provides an indication of the data values of the remaining words of the output page. The time necessary to read and verify a repeating test pattern can be reduced as only one word of each output page need be read to determine the ability of the memory device to accurately write and store data values. The memory devices include data compression circuits to compare data values for each bit location of each word of the output page. Output is selectively disabled if a bit location for one word of the output page has a data value differing from any remaining word of the output page.

公开(公告)号：US06717862B2

公开(公告)日：2004-04-06

申请号：US10229921

申请日：2002-08-28

申请人： Giovanni Naso ,  Giovanni Santin ,  Pasquale Pistilli

发明人： Giovanni Naso ,  Giovanni Santin ,  Pasquale Pistilli

IPC分类号： G11C1604

CPC分类号： G11C29/12005 ,  G11C16/04 ,  G11C16/16 ,  G11C29/12

摘要： Methods and apparatus to facilitate erasure of multiple sectors of a memory device without the need for externally-supplied erase potentials are advantageous for device testing. During a scan of sector addresses, sector tagging blocks of a memory device provide an output signal to a write state machine indicating whether the addressed sector is tagged for erasure. The sector tagging blocks facilitate resetting of tags on a global basis and setting of tags on a single, bank-wide and/or global basis. Once initiated, the erase operation proceeds to erase each tagged sector of the memory device in sequence without the need for externally-supplied erase potentials and without the need for further direction of the tester hardware. The methods are particularly useful for erasing all sectors of a memory device or all sectors of one memory bank of the memory device.

摘要翻译： 便于擦除存储器件的多个扇区而不需要外部提供的擦除电位的方法和装置对于器件测试是有利的。 在扇区地址的扫描期间，存储器件的扇区标记块向写入状态机提供指示被寻址扇区是否被标记为擦除的输出信号。 扇区标记块有助于在全球范围内重置标签，并在单个银行范围和/或全局基础上设置标签。 一旦启动，擦除操作继续进行以顺序地擦除存储器件的每个标记扇区，而不需要外部提供的擦除电位，并且不需要测试仪硬件的进一步的方向。 这些方法对于擦除存储器件的所有扇区或存储器件的一个存储器组的所有扇区特别有用。