公开(公告)号：US20130051141A1

公开(公告)日：2013-02-28

申请号：US13219439

申请日：2011-08-26

申请人： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

发明人： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

IPC分类号： G11C16/04

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.

摘要翻译： 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

公开(公告)号：US07635991B2

公开(公告)日：2009-12-22

申请号：US11415980

申请日：2006-05-02

申请人： Girolamo Gallo ,  Giulio Marotta ,  Giovanni Naso

发明人： Girolamo Gallo ,  Giulio Marotta ,  Giovanni Naso

IPC分类号： H03K17/16

CPC分类号： H03K17/164

摘要： Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.

摘要翻译： 用于调整输出缓冲器的缓冲器强度以匹配其电容负载的装置和方法使用多级输出缓冲器的选择性使能级。 用户可以选择默认的容性负载，或通过启用多级输出缓冲器的一个或多个级来调整强度。

公开(公告)号：US20090067252A1

公开(公告)日：2009-03-12

申请号：US12032928

申请日：2008-02-18

申请人： Giovanni Naso ,  Stefano Donnola

发明人： Giovanni Naso ,  Stefano Donnola

IPC分类号： G11C16/06 ,  G11C17/18

CPC分类号： G11C17/18

摘要： One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment includes detecting a signal indicating whether a voltage used during operation of at least one of a number of fuse circuits has reached a threshold level, initializing at least one of the number of fuse circuits in response to detecting that the voltage has reached the threshold level, and reading an output of at least one of the number of fuse circuits at least partially in response to a detected state change of an output of the at least one initialized fuse circuit.

摘要翻译： 本公开的一个或多个实施例提供了用于操作具有熔丝电路的存储器件的方法，装置和系统。 一种方法实施例包括检测指示在多个熔丝电路中的至少一个的操作期间使用的电压是否已经达到阈值电平的信号，响应于检测到电压已达到阈值而初始化多个熔丝电路中的至少一个 至少部分地响应于所述至少一个初始化熔丝电路的输出的检测到的状态改变来读取所述多个熔丝电路中的至少一个的输出。

公开(公告)号：US20070022332A1

公开(公告)日：2007-01-25

申请号：US11519415

申请日：2006-09-12

申请人： Giuliano Imondi ,  Giovanni Naso

发明人： Giuliano Imondi ,  Giovanni Naso

IPC分类号： G01R31/28

CPC分类号： G11C16/3445 ,  G11C16/344

摘要： Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.

摘要翻译： 操作存储器件的存储器件和方法在擦除验证操作期间提供使用不同的电位，便于正常擦除操作和随后的擦除检查操作。 与普通擦除操作相比，这种装置和方法便于使用缩写的过程随后检查擦除的存储器单元的数据增益。

公开(公告)号：US07064582B2

公开(公告)日：2006-06-20

申请号：US10701090

申请日：2003-11-04

申请人： Girolamo Gallo ,  Giulio Marotta ,  Giovanni Naso

发明人： Girolamo Gallo ,  Giulio Marotta ,  Giovanni Naso

IPC分类号： H03K17/16

CPC分类号： H03K17/164

摘要： Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.

公开(公告)号：US20050237804A1

公开(公告)日：2005-10-27

申请号：US11170880

申请日：2005-06-30

申请人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

发明人： Giovanni Naso ,  Pietro Piersimoni ,  Tommaso Vali

IPC分类号： G11C7/24 ,  G11C16/00 ,  G11C16/04 ,  G11C16/22 ,  G11C17/00

CPC分类号： G11C7/24 ,  G11C16/22 ,  G11C2029/4402

摘要： An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.

公开(公告)号：US06845029B2

公开(公告)日：2005-01-18

申请号：US10642959

申请日：2003-08-18

申请人： Giovanni Santin ,  Giovanni Naso

发明人： Giovanni Santin ,  Giovanni Naso

IPC分类号： G11C16/20 ,  G11C16/26 ,  G11C17/18 ,  G11C29/00 ,  G11C17/00

CPC分类号： G11C29/789 ,  G11C16/0441 ,  G11C16/20 ,  G11C16/26 ,  G11C17/18

摘要： Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory applications. The fuse circuits include a floating-gate memory cell for storing a data value and a fuse latch to hold and transfer the data value of the floating-gate memory cell at power-up or upon request. A latch driver circuit can write data values to the fuse latch without affecting the data value stored in the floating-gate memory cell. The fuse circuits can further utilize the same structure, pitch, bit-line organization and word-line organization as the memory device's memory array. As the fuse circuits can utilize the same structure and organization, the data value of the fuse circuit can be programmed, erased and read using the same data path as the regular memory array.

摘要翻译： 基于单个闪存单元或浮动栅极存储单元的保险丝电路适用于存储器件，特别是在低电压闪速存储器应用中。 熔丝电路包括用于存储数据值的浮动栅存储器单元和用于在通电或根据要求保持和传送浮栅存储单元的数据值的熔丝锁存器。 锁存驱动器电路可以将数据值写入熔丝锁存器而不影响存储在浮动栅极存储单元中的数据值。 熔丝电路可以进一步利用与存储器件的存储器阵列相同的结构，间距，位线组织和字线组织。 由于熔丝电路可以使用相同的结构和组织，因此可以使用与常规存储器阵列相同的数据路径对熔丝电路的数据值进行编程，擦除和读取。

公开(公告)号：US06785162B2

公开(公告)日：2004-08-31

申请号：US10192334

申请日：2002-07-10

申请人： Giovanni Naso ,  Elio D'Ambrosio

发明人： Giovanni Naso ,  Elio D'Ambrosio

IPC分类号： G11C1604

CPC分类号： G11C29/46 ,  G11C16/04 ,  G11C29/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

摘要翻译： 本发明的实施例包括将集成电路放入测试模式的接口电路和解码器来解码提供给集成电路的一个或多个命令。 解码器包括子电路，并且每个子电路具有串联耦合的多个晶体管。 串联耦合的晶体管具有耦合到时钟信号的控制栅极或表示命令的几个反相或非反相命令信号之一。 每个子电路中的控制栅极被耦合，使得时钟信号和命令信号的独特模式将导通所有晶体管以解码该命令。 每个子电路能够解码单个命令。 子电路具有比p沟道晶体管更多的n沟道晶体管的逻辑比。 解码器可以通过通孔的灵活放置来制造。

公开(公告)号：US07657802B2

公开(公告)日：2010-02-02

申请号：US11780734

申请日：2007-07-20

申请人： Giovanni Naso

发明人： Giovanni Naso

IPC分类号： G11C29/00

CPC分类号： G11C7/1006 ,  G11C29/02 ,  G11C29/40

摘要： A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first series combination compares the values in the predetermined bit position to determine if they are all a logical zero. A second series combination of bit match circuits compares the same predetermined bit position in the data words. The second series combination compares the values to determine if they are all a logical one. If either condition is true, the value of the bit is output through an output buffer. If both conditions are false, the output buffer is placed in a high impedance state to indicate an error condition exists in that bit position.

摘要翻译： 位匹配电路的第一串联组合比较了压缩操作中涉及的数据字中的预定位位置。 第一系列组合比较预定位位置中的值，以确定它们是否都是逻辑零。 位匹配电路的第二串联组合比较数据字中相同的预定位位置。 第二个系列组合比较这些值，以确定它们是否都是逻辑的。 如果任一条件为真，则通过输出缓冲区输出该位的值。 如果两个条件均为假，则输出缓冲器处于高阻抗状态，以指示该位位置存在错误条件。

公开(公告)号：US20080086604A1

公开(公告)日：2008-04-10

申请号：US11642038

申请日：2006-12-19

申请人： Giovanni Naso ,  Stefano Donnola

发明人： Giovanni Naso ,  Stefano Donnola

IPC分类号： G06F13/00

CPC分类号： G06F13/16 ,  Y02D10/14

摘要： In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.

摘要翻译： 在各种实施例中，装置和系统以及方法可以包括增强型寄存器以向存储器阵列提供致动器信号，增强型寄存器包括第一存储器件，其包括第一使能输入，耦合到寄存器数据的第一数据输入 输入和第一存储器件输出，第一存储器件输出以耦合到存储器阵列，并且增强寄存器以包括第二存储器件，其包括第二使能输入，耦合到寄存器数据输入的第二数据输入和第二存储器 存储器件输出，其中第二存储器件输出提供指示何时来自第一存储器件输出的一个或多个致动器信号将被耦合到寄存器数据输入的第一输出信号。